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Title:
Author:
Edward S. Davidson: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. David W. L. Yen, Janak H. Patel, Edward S. Davidson
    Memory Interference in Synchronous Multiprocessor Systems. [Citation Graph (1, 0)][DBLP]
    IEEE Trans. Computers, 1982, v:31, n:11, pp:1116-1121 [Journal]
  2. Gheith A. Abandah, Edward S. Davidson
    Origin 2000 Design Enhancements for Communication Intensive Applications. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1998, pp:30-39 [Conf]
  3. Mikhail Smelyanskiy, Gary S. Tyson, Edward S. Davidson
    Register Queues: A New Hardware/Software Approach to Efficient Software Pipelining. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2000, pp:3-12 [Conf]
  4. William H. Mangione-Smith, Santosh G. Abraham, Edward S. Davidson
    Vector Register Design for Polycyclic Vector Scheduling. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1991, pp:154-163 [Conf]
  5. Mikhail Smelyanskiy, Scott A. Mahlke, Edward S. Davidson
    Probabilistic Predicate-Aware Modulo Scheduling. [Citation Graph (0, 0)][DBLP]
    CGO, 2004, pp:151-162 [Conf]
  6. Mikhail Smelyanskiy, Scott A. Mahlke, Edward S. Davidson, Hsien-Hsin S. Lee
    Predicate-Aware Scheduling: A Technique for Reducing Resource Constraints. [Citation Graph (0, 0)][DBLP]
    CGO, 2003, pp:169-178 [Conf]
  7. Edward S. Davidson
    A Broader Range of Possible Answers to the Issues Raised by RISC. [Citation Graph (0, 0)][DBLP]
    COMPCON, 1986, pp:313-315 [Conf]
  8. Andrew R. Pleszkun, Gurindar S. Sohi, Bassam Z. Kahhaleh, Edward S. Davidson
    Features of the Structured Memory Access (SMA) Architecture. [Citation Graph (0, 0)][DBLP]
    COMPCON, 1986, pp:259-265 [Conf]
  9. Murali Annavaram, Jignesh M. Patel, Edward S. Davidson
    Call Graph Prefetching for Database Applications. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:281-0 [Conf]
  10. Viji Srinivasan, Edward S. Davidson, Gary S. Tyson, Mark J. Charney, Thomas R. Puzak
    Branch History Guided Instruction Prefetching. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:291-300 [Conf]
  11. Chuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah
    Using constraint geometry to determine maximum rate pipeline clocking. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:142-148 [Conf]
  12. Jude A. Rivers, Edward S. Tam, Edward S. Davidson
    On Effective Data Supply For Multi-Issue Processors. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:519-528 [Conf]
  13. Karem A. Sakallah, Trevor N. Mudge, Timothy M. Burks, Edward S. Davidson
    Optimal Clocking of Circular Pipelines. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:642-650 [Conf]
  14. Edward S. Tam, Stevan A. Vlaovic, Gary S. Tyson, Edward S. Davidson
    Allocation by Conflict: A Simple Effective Multilateral Cache Management Scheme. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:133-141 [Conf]
  15. Stevan A. Vlaovic, Edward S. Davidson
    TAXI: Trace Analysis for X86 Interpretation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:508-514 [Conf]
  16. John-David Wellman, Edward S. Davidson
    The resource conflict methodology for early-stage design space exploration of superscalar RISC processors. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:110-0 [Conf]
  17. Tien-Pao Shih, Edward S. Davidson
    Grouping Array Layouts to Reduce Communication and Improve Locality of Parallel Programs. [Citation Graph (0, 0)][DBLP]
    ICPADS, 1994, pp:558-566 [Conf]
  18. Santosh G. Abraham, Edward S. Davidson
    A Communication Model for Optimizing Hierarchical Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    ICPP, 1986, pp:467-474 [Conf]
  19. Eric L. Boyd, Waqar Azeem, Hsien-Hsin S. Lee, Tien-Pao Shih, Shih-Hao Hung, Edward S. Davidson
    A Hierarchical Approach to Modeling and Improving the Performance of Scientific Applications on the KSR1. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1994, pp:188-192 [Conf]
  20. Timothy A. Davis, Edward S. Davidson
    PSOLVE : A Concurrent Algorithm for Solving Sparse Systems of Linear Equations. [Citation Graph (0, 0)][DBLP]
    ICPP, 1987, pp:483-490 [Conf]
  21. Jeff Konicek, Tracy Tilton, Alexander V. Veidenbaum, Chuan-Qi Zhu, Edward S. Davidson, Ruppert A. Downing, Michael J. Haney, Manish Sharma, Pen-Chung Yew, P. Michael Farmwald, David J. Kuck, Daniel M. Lavery, Robert A. Lindsey, D. Pointer, John T. Andrews, Thomas Beck, T. Murphy, Stephen W. Turner, Nancy J. Warter
    The Organization of the Cedar System. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1991, pp:49-56 [Conf]
  22. Andrew R. Pleszkun, Edward S. Davidson
    Structured Memory Access Architecture. [Citation Graph (0, 0)][DBLP]
    ICPP, 1983, pp:461-471 [Conf]
  23. Jude A. Rivers, Edward S. Davidson
    Reducing Conflicts in Direct-Mapped Caches with a Temporality-Based Design. [Citation Graph (0, 0)][DBLP]
    ICPP, Vol. 1, 1996, pp:154-163 [Conf]
  24. Eric L. Boyd, Edward S. Davidson
    Communication in the KSR1 MPP: performance evaluation using synthetic workload experiments. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1994, pp:166-175 [Conf]
  25. Eric L. Boyd, John-David Wellman, Santosh G. Abraham, Edward S. Davidson
    Evaluating the Communication Performance of MPPs Using Synthetic Sparse Matrix Multiplication Workloads. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1993, pp:240-250 [Conf]
  26. Alexandre E. Eichenberger, Edward S. Davidson, Santosh G. Abraham
    Optimum Modulo Schedules for Minimum Register Requirements. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1995, pp:31-40 [Conf]
  27. Waleed Meleis, Edward S. Davidson
    Optimal local register allocation for a multiple-issue machine. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1994, pp:107-116 [Conf]
  28. William H. Mangione-Smith, Santosh G. Abraham, Edward S. Davidson
    Register requirements of pipelined processors. [Citation Graph (0, 0)][DBLP]
    ICS, 1992, pp:260-271 [Conf]
  29. Jude A. Rivers, Edward S. Tam, Gary S. Tyson, Edward S. Davidson, Matthew K. Farrens
    Utilizing Reuse Information in Data Cache Management. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1998, pp:449-456 [Conf]
  30. J. H. Tang, Edward S. Davidson
    An evaluation of Cray X-MP performance on vectorizable Livermore FORTRAN kernels. [Citation Graph (0, 0)][DBLP]
    ICS, 1988, pp:510-518 [Conf]
  31. Karen A. Tomko, Edward S. Davidson
    Profile Driven Weighted Decomposition. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1996, pp:165-172 [Conf]
  32. Stevan A. Vlaovic, Edward S. Davidson
    Boosting trace cache performance with nonhead miss speculation. [Citation Graph (0, 0)][DBLP]
    ICS, 2002, pp:179-188 [Conf]
  33. Gheith A. Abandah, Edward S. Davidson
    Modeling the Communication Performance of the IBM SP2. [Citation Graph (0, 0)][DBLP]
    IPPS, 1996, pp:249-257 [Conf]
  34. Gheith A. Abandah, Edward S. Davidson
    Configuration Independent Analysis for Characterizing Shared-Memory Applications. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP, 1998, pp:485-491 [Conf]
  35. Daniel Windheiser, Eric L. Boyd, Eric Hao, Santosh G. Abraham, Edward S. Davidson
    KSR 1 Multiprocessor: Analysis of Latency Hiding Techniques in a Sparse Solver. [Citation Graph (0, 0)][DBLP]
    IPPS, 1993, pp:454-461 [Conf]
  36. Gheith A. Abandah, Edward S. Davidson
    Effects of Architectural and Technological Advances on the HP/Convex Exemplar's Memory and Communication Performance. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:318-329 [Conf]
  37. Murali Annavaram, Jignesh M. Patel, Edward S. Davidson
    Data prefetching by dependence graph precomputation. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:52-61 [Conf]
  38. Pradip Bose, Edward S. Davidson
    Design of Instruction Set Architectures for Support of High-Level Languages . [Citation Graph (0, 0)][DBLP]
    ISCA, 1984, pp:198-206 [Conf]
  39. Eric L. Boyd, Edward S. Davidson
    Hierarchical Performance Modeling with MACS: A Case Study of the Convex C-240. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:203-212 [Conf]
  40. Edward S. Davidson
    A Multiple Stream Microprocessor Prototype System: AMP-1. [Citation Graph (0, 0)][DBLP]
    ISCA, 1980, pp:9-16 [Conf]
  41. Dan W. Hammerstrom, Edward S. Davidson
    Information Content of CPU Memory Referencing Behavior. [Citation Graph (0, 0)][DBLP]
    ISCA, 1977, pp:184-192 [Conf]
  42. Peter Y.-T. Hsu, Edward S. Davidson
    Highly Concurrent Scalar Processing. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:386-395 [Conf]
  43. Peter Y.-T. Hsu, Joseph T. Rahmeh, Edward S. Davidson, Jacob A. Abraham
    TIDBITS: Speedup Via Time-Delay Bit-Slicing in ALU Design for VLSI Technology. [Citation Graph (0, 0)][DBLP]
    ISCA, 1985, pp:28-35 [Conf]
  44. David J. Kuck, Edward S. Davidson, Duncan H. Lawrie, Ahmed H. Sameh, Chuan-Qi Zhu
    The Cedar System and an Initial Performance Study. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:462-472 [Conf]
  45. David J. Kuck, Edward S. Davidson, Duncan H. Lawrie, Ahmed H. Sameh, Chuan-Qi Zhu, Alexander V. Veidenbaum, Jeff Konicek, Pen-Chung Yew, Kyle Gallivan, William Jalby, Harry A. G. Wijshoff, Randall Bramley, U. M. Yang, Perry A. Emrath, David A. Padua, Rudolf Eigenmann, Jay Hoeflinger, Greg Jaxon, Zhiyuan Li, T. Murphy, John T. Andrews, Stephen W. Turner
    The Cedar System and an Initial Performance Study. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:213-223 [Conf]
  46. Geoffrey D. McNiven, Edward S. Davidson
    Analysis of Memory Referencing Behavior For Design of Local Memories. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:56-63 [Conf]
  47. Janak H. Patel, Edward S. Davidson
    Improving the Throughput of a Pipeline by Insertion of Delays. [Citation Graph (0, 0)][DBLP]
    ISCA, 1976, pp:159-164 [Conf]
  48. Janak H. Patel, Edward S. Davidson
    Improving the Throughput of a Pipeline by Insertion of Delays. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:132-137 [Conf]
  49. Gurindar S. Sohi, Edward S. Davidson, Janak H. Patel
    An Efficient LISP-Execution Architecture with a New Representation for List Structures. [Citation Graph (0, 0)][DBLP]
    ISCA, 1985, pp:91-98 [Conf]
  50. Alexander V. Veidenbaum, Pen-Chung Yew, David J. Kuck, Constantine D. Polychronopoulos, David A. Padua, Edward S. Davidson, Kyle Gallivan
    Retrospective: The Cedar System. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:89-91 [Conf]
  51. Phil C. C. Yeh, Janak H. Patel, Edward S. Davidson
    Performance of Shared Cache for Parallel-Pipelined Computer Systems [Citation Graph (0, 0)][DBLP]
    ISCA, 1983, pp:117-123 [Conf]
  52. Edward S. Tam, Jude A. Rivers, Gary S. Tyson, Edward S. Davidson
    mlcache: A Flexible Multi-Lateral Cache Simulator. [Citation Graph (0, 0)][DBLP]
    MASCOTS, 1998, pp:19-26 [Conf]
  53. Alexandre E. Eichenberger, Edward S. Davidson
    Register allocation for predicated code. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:180-191 [Conf]
  54. Alexandre E. Eichenberger, Edward S. Davidson
    Stage scheduling: a technique to reduce the register requirements of a modulo schedule. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:338-349 [Conf]
  55. Alexandre E. Eichenberger, Edward S. Davidson, Santosh G. Abraham
    Minimum register requirements for a modulo schedule. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:75-84 [Conf]
  56. Jude A. Rivers, Gary S. Tyson, Edward S. Davidson, Todd M. Austin
    On High-Bandwidth Data Cache Design for Multi-Issue Processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1997, pp:46-56 [Conf]
  57. Stevan A. Vlaovic, Edward S. Davidson, Gary S. Tyson
    Improving BTB performance in the presence of DLLs. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:77-86 [Conf]
  58. Alexandre E. Eichenberger, Edward S. Davidson
    A Reduced Multipipeline Machine Description that Preserves Scheduling Constraints. [Citation Graph (0, 0)][DBLP]
    PLDI, 1996, pp:12-22 [Conf]
  59. Alexandre E. Eichenberger, Edward S. Davidson
    Efficient Formulation for Optimal Modulo Schedulers. [Citation Graph (0, 0)][DBLP]
    PLDI, 1997, pp:194-205 [Conf]
  60. Daniel L. Weller, Edward S. Davidson
    Optimal Searching Algorihtms for Parallel Pipelined Computers. [Citation Graph (0, 0)][DBLP]
    Sagamore Computer Conference, 1974, pp:291-305 [Conf]
  61. J. H. Tang, Edward S. Davidson, J. Tong
    Polycyclic Vector scheduling vs. Chaining on 1-Port Vector supercomputers. [Citation Graph (0, 0)][DBLP]
    SC, 1988, pp:122- [Conf]
  62. Waleed Meleis, Edward S. Davidson
    Dual-Issue Scheduling with Spills for Binary Trees. [Citation Graph (0, 0)][DBLP]
    SODA, 1999, pp:678-686 [Conf]
  63. B. Kumar, Edward S. Davidson
    Performance Evaluation of Highly Concurrent Computers by Deterministic Simulation. [Citation Graph (0, 0)][DBLP]
    Commun. ACM, 1978, v:21, n:11, pp:904-913 [Journal]
  64. B. Kumar, Edward S. Davidson
    Computer System Design Using a Hierarchical Approach to Performance Evaluation. [Citation Graph (0, 0)][DBLP]
    Commun. ACM, 1980, v:23, n:9, pp:511-521 [Journal]
  65. William H. Mangione-Smith, Santosh G. Abraham, Edward S. Davidson
    A Performance Comparison of the IBM RS/6000 and the Astronautics ZS-1. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1991, v:24, n:1, pp:39-46 [Journal]
  66. Jude A. Rivers, Edward S. Davidson
    Performance Issues in Integrating Temporality-Based Caching with Prefetching. [Citation Graph (0, 0)][DBLP]
    Perform. Eval., 1996, v:27, n:4, pp:189-207 [Journal]
  67. Faye A. Briggs, Edward S. Davidson
    Organization of Semiconductor Memories for Parallel-Pipelined Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1977, v:26, n:2, pp:162-169 [Journal]
  68. Timothy A. Davis, Edward S. Davidson
    Pairwise Reduction for the Direct, Parallel Solution of Sparse, Unsymmetric Sets of Linear Equations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:12, pp:1648-1654 [Journal]
  69. Philip G. Emma, Edward S. Davidson
    Characterization of Branch and Data Dependencies in Programs for Evaluating Pipeline Performance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:7, pp:859-875 [Journal]
  70. Viji Srinivasan, Edward S. Davidson, Gary S. Tyson
    A Prefetch Taxonomy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:2, pp:126-140 [Journal]
  71. Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson
    Active Management of Data Caches by Exploiting Reuse Information. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:11, pp:1244-1259 [Journal]
  72. G. X. Tyson, M. Smelyanskyi, Edward S. Davidson
    Evaluating the Use of Register Queues in Software Pipelined Loops. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:8, pp:769-783 [Journal]
  73. Phil C. C. Yeh, Janak H. Patel, Edward S. Davidson
    Shared Cache for Multiple-Stream Computer Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:1, pp:38-47 [Journal]
  74. Chuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah
    Maximum rate single-phase clocking of a closed pipeline including wave pipelining, stoppability, and startability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1526-1545 [Journal]
  75. Karem A. Sakallah, Trevor N. Mudge, Timothy M. Burks, Edward S. Davidson
    Synchronization of pipelines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:8, pp:1132-1146 [Journal]
  76. Murali Annavaram, Jignesh M. Patel, Edward S. Davidson
    Call graph prefetching for database applications. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Comput. Syst., 2003, v:21, n:4, pp:412-444 [Journal]
  77. Gheith A. Abandah, Edward S. Davidson
    Characterizing Distributed Shared Memory Performance: A Case Study of the Convex SPP1000. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1998, v:9, n:2, pp:206-216 [Journal]
  78. Robert L. Budzinski, Edward S. Davidson
    A Comparison of Dynamic and Static Virtual Memory Allocation Algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 1981, v:7, n:1, pp:122-131 [Journal]
  79. Robert L. Budzinski, Edward S. Davidson, Wataru Mayeda, Harold S. Stone
    DMIN: An Algorithm for Computing the Optimal Dynamic Allocation in a Virtual Memory Computer. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 1981, v:7, n:1, pp:113-121 [Journal]

  80. Evaluating database management systems. [Citation Graph (, )][DBLP]


  81. A freespace crossbar for multi-core processors. [Citation Graph (, )][DBLP]


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