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Manuel E. Acacio: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Manuel E. Acacio, José González, José M. García, José Duato
    The Use of Prediction for Accelerating Upgrade Misses in cc-NUMA Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2002, pp:155-164 [Conf]
  2. Manuel E. Acacio, Óscar Cánovas Reverte, José M. García, Pedro E. López-de-Teruel
    An Evaluation of Parallel Computing in PC Clusters with Fast Ethernet. [Citation Graph (0, 0)][DBLP]
    ACPC, 1999, pp:570-571 [Conf]
  3. Antonio Flores, Juan L. Aragón, Manuel E. Acacio
    Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures. [Citation Graph (0, 0)][DBLP]
    AINA Workshops (1), 2007, pp:752-757 [Conf]
  4. Alberto Ros, Manuel E. Acacio, José M. García
    An efficient cache design for scalable glueless shared-memory multiprocessors. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2006, pp:321-330 [Conf]
  5. Alberto Ros, Manuel E. Acacio, José M. García
    A Novel Lightweight Directory Architecture for Scalable Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2005, pp:582-591 [Conf]
  6. Manuel E. Acacio, José González, José M. García, José Duato
    A New Scalable Directory Architecture for Large-Scale Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:97-106 [Conf]
  7. Francisco J. Villa, Manuel E. Acacio, José M. García
    Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture. [Citation Graph (0, 0)][DBLP]
    HPCC, 2005, pp:213-222 [Conf]
  8. Francisco J. Villa, Manuel E. Acacio, José M. García
    On the Evaluation of x86 Web Servers Using Simics: Limitations and Trade-Offs. [Citation Graph (0, 0)][DBLP]
    International Conference on Computational Science, 2004, pp:541-544 [Conf]
  9. Manuel E. Acacio, José González, José M. García, José Duato
    A Novel Approach to Reduce L2 Miss Latency in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  10. Pedro E. López-de-Teruel, José M. García, Manuel E. Acacio, Óscar Cánovas Reverte
    P-EDR: An Algorithm for Parallel Implementation of Parzen Density Estimation from Uncertain Observations. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP, 1999, pp:563-568 [Conf]
  11. Manuel E. Acacio, José González, José M. García, José Duato
    Reducing the Latency of L2 Misses in Shared-Memory Multiprocessors through On-Chip Directory Integration. [Citation Graph (0, 0)][DBLP]
    PDP, 2002, pp:368-375 [Conf]
  12. Ricardo Fernández, José M. García, Gregorio Bernabé, Manuel E. Acacio
    Optimizing a 3D-FWT Video Encoder for SMPs and HyperThreading Architectures. [Citation Graph (0, 0)][DBLP]
    PDP, 2005, pp:76-83 [Conf]
  13. Manuel E. Acacio, José M. García, Pedro E. López-de-Teruel
    A Performance Evaluation of P-EDR in Different Parallel Environments. [Citation Graph (0, 0)][DBLP]
    PDPTA, 1999, pp:744-750 [Conf]
  14. Manuel E. Acacio, Pedro E. López-de-Teruel, José M. García, Óscar Cánovas Reverte
    The MPI-Delphi Interface: A Visual Programming Environment for Clusters of Workstations. [Citation Graph (0, 0)][DBLP]
    PDPTA, 1999, pp:1730-1736 [Conf]
  15. Pedro E. López-de-Teruel, José M. García, Manuel E. Acacio
    The Parallel EM Algorithm and its Applications in Computer Vision. [Citation Graph (0, 0)][DBLP]
    PDPTA, 1999, pp:571-578 [Conf]
  16. Manuel E. Acacio, José González, José M. García, José Duato
    Owner prediction for accelerating cache-to-cache transfer misses in a cc-NUMA architecture. [Citation Graph (0, 0)][DBLP]
    SC, 2002, pp:1-12 [Conf]
  17. Manuel E. Acacio, Óscar Cánovas Reverte, José M. García, Pedro E. López-de-Teruel
    MPI-Delphi: an MPI implementation for visual programming environments and heterogeneous computing. [Citation Graph (0, 0)][DBLP]
    Future Generation Comp. Syst., 2002, v:18, n:3, pp:317-333 [Journal]
  18. Francisco J. Villa, Manuel E. Acacio, J. M. García
    Evaluating IA-32 web servers through simics: a practical experience. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2005, v:51, n:4, pp:251-264 [Journal]
  19. Gregorio Bernabé, Ricardo Fernández, José M. García, Manuel E. Acacio, José González
    An efficient implementation of a 3D wavelet transform based encoder on hyper-threading technology. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 2007, v:33, n:1, pp:54-72 [Journal]
  20. Manuel E. Acacio, José González, José M. García, José Duato
    An Architecture for High-Performance Scalable Shared-Memory Multiprocessors Exploiting On-Chip Integration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2004, v:15, n:8, pp:755-768 [Journal]
  21. Manuel E. Acacio, José González, José M. García, José Duato
    A Two-Level Directory Architecture for Highly Scalable cc-NUMA Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2005, v:16, n:1, pp:67-79 [Journal]
  22. Francisco J. Villa, Manuel E. Acacio, José M. García
    On the Evaluation of Dense Chip-Multiprocessor Architectures. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:21-27 [Conf]

  23. Dealing with Traffic-Area Trade-Off in Direct Coherence Protocols for Many-Core CMPs. [Citation Graph (, )][DBLP]


  24. Scalable Directory Organization for Tiled CMP Architectures. [Citation Graph (, )][DBLP]


  25. Efficient and scalable barrier synchronization for many-core CMPs. [Citation Graph (, )][DBLP]


  26. Multicore Platforms for Scientific Computing: Cell BE and NVIDIA Tesla. [Citation Graph (, )][DBLP]


  27. A fault-tolerant directory-based cache coherence protocol for CMP architectures. [Citation Graph (, )][DBLP]


  28. Fast and Efficient Synchronization and Communication Collective Primitives for Dual Cell-Based Blades. [Citation Graph (, )][DBLP]


  29. Directory-Based Conflict Detection in Hardware Transactional Memory. [Citation Graph (, )][DBLP]


  30. Distance-aware round-robin mapping for large NUCA caches. [Citation Graph (, )][DBLP]


  31. Efficient Message Management in Tiled CMP Architectures Using a Heterogeneous Interconnection Network. [Citation Graph (, )][DBLP]


  32. Direct Coherence: Bringing Together Performance and Scalability in Shared-Memory Multiprocessors. [Citation Graph (, )][DBLP]


  33. Fault-Tolerant Cache Coherence Protocols for CMPs: Evaluation and Trade-Offs. [Citation Graph (, )][DBLP]


  34. A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures. [Citation Graph (, )][DBLP]


  35. Characterizing the Basic Synchronization and Communication Operations in Dual Cell-Based Blades. [Citation Graph (, )][DBLP]


  36. Address Compression and Heterogeneous Interconnects for Energy-Efficient High-Performance in Tiled CMPs. [Citation Graph (, )][DBLP]


  37. DiCo-CMP: Efficient cache coherency in tiled CMP architectures. [Citation Graph (, )][DBLP]


  38. Speculation-based conflict resolution in hardware transactional memory. [Citation Graph (, )][DBLP]


  39. CellStats: A Tool to Evaluate the Basic Synchronization and Communication Operations of the Cell BE. [Citation Graph (, )][DBLP]


  40. Characterization of Conflicts in Log-Based Transactional Memory (LogTM). [Citation Graph (, )][DBLP]


  41. A Parallel Implementation of the 2D Wavelet Transform Using CUDA. [Citation Graph (, )][DBLP]


  42. Energy-Efficient Hardware Prefetching for CMPs Using Heterogeneous Interconnects. [Citation Graph (, )][DBLP]


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