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Title:
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José González: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Manuel E. Acacio, José González, José M. García, José Duato
    The Use of Prediction for Accelerating Upgrade Misses in cc-NUMA Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2002, pp:155-164 [Conf]
  2. José González, Antonio González
    Control-Flow Speculation through Value Prediction for Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1999, pp:57-65 [Conf]
  3. Gregorio Bernabé, José González, José M. García, José Duato
    Memory Conscious 3D Wavelet Transform. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2002, pp:108-113 [Conf]
  4. José González, Antonio González
    Memory Address Prediction for Data Speculation. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1997, pp:1084-1091 [Conf]
  5. Juan L. Aragón, José González, José M. García, Antonio González
    Confidence Estimation for Branch Prediction Reversal. [Citation Graph (0, 0)][DBLP]
    HiPC, 2001, pp:214-223 [Conf]
  6. Manuel E. Acacio, José González, José M. García, José Duato
    A New Scalable Directory Architecture for Large-Scale Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:97-106 [Conf]
  7. Juan L. Aragón, José González, Antonio González
    Power-Aware Control Speculation through Selective Throttling. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:103-112 [Conf]
  8. Antonio González, José González, Mateo Valero
    Virtual-Physical Registers. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:175-184 [Conf]
  9. Pedro Chaparro, Grigorios Magklis, José González, Antonio González
    Distributing the Frontend for Temperature Reduction. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:61-70 [Conf]
  10. Juan L. Aragón, José González, José M. García, Antonio González
    Selective Branch Prediction Reversal By Correlating with Data Values and Control Flow. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:228-233 [Conf]
  11. Pedro Chaparro, José González, Antonio González
    Thermal-Aware Clustered Microarchitectures. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:48-53 [Conf]
  12. José González, Antonio González
    Dynamic Cluster Resizing. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:375-0 [Conf]
  13. Grigorios Magklis, José González, Antonio González
    Frontend Frequency-Voltage Adaptation for Optimal Energy-Delay^2. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:250-255 [Conf]
  14. Juan L. Aragón, José González, Antonio González, James E. Smith
    Dual path instruction processing. [Citation Graph (0, 0)][DBLP]
    ICS, 2002, pp:220-229 [Conf]
  15. José González, Antonio González
    Speculative Execution via Address Prediction and Data Prefetching. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1997, pp:196-203 [Conf]
  16. José González, Antonio González
    The Potential of Data Value Speculation to Boost ILP. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1998, pp:21-28 [Conf]
  17. Fernando Latorre, José González, Antonio González
    Back-end assignment schemes for clustered multithreaded processors. [Citation Graph (0, 0)][DBLP]
    ICS, 2004, pp:316-325 [Conf]
  18. Manuel E. Acacio, José González, José M. García, José Duato
    A Novel Approach to Reduce L2 Miss Latency in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  19. Grigorios Magklis, Pedro Chaparro, José González, Antonio González
    Independent front-end and back-end dynamic voltage scaling for a GALS microarchitecture. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:49-54 [Conf]
  20. Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals
    Delaying Physical Register Allocation through Virtual-Physical Registers. [Citation Graph (0, 0)][DBLP]
    MICRO, 1999, pp:186-0 [Conf]
  21. Nigel P. Topham, Antonio González, José González
    The Design and Performance of a Conflict-Avoiding Cache. [Citation Graph (0, 0)][DBLP]
    MICRO, 1997, pp:71-80 [Conf]
  22. Javier Cuenca, Domingo Giménez, José González, Jack Dongarra, Kenneth Roche
    Automatic Optimisation of Parallel Linear Algebra Routines in Systems with Variable Load. [Citation Graph (0, 0)][DBLP]
    PDP, 2003, pp:409-416 [Conf]
  23. Manuel E. Acacio, José González, José M. García, José Duato
    Reducing the Latency of L2 Misses in Shared-Memory Multiprocessors through On-Chip Directory Integration. [Citation Graph (0, 0)][DBLP]
    PDP, 2002, pp:368-375 [Conf]
  24. Gregorio Bernabé, José M. García, José González
    Reducing 3D Wavelet Transform Execution Time through the Streaming SIMD Extensions. [Citation Graph (0, 0)][DBLP]
    PDP, 2003, pp:49-56 [Conf]
  25. Javier Cuenca, Domingo Giménez, José González
    Towards the Design of an Automatically Tuned Linear Algebra Library. [Citation Graph (0, 0)][DBLP]
    PDP, 2002, pp:201-0 [Conf]
  26. Javier Cuenca, Luis-Pedro García, Domingo Giménez, José González, Antonio M. Vidal
    Empirical Modelling of Parallel Linear Algebra Routines. [Citation Graph (0, 0)][DBLP]
    PPAM, 2003, pp:169-174 [Conf]
  27. Manuel E. Acacio, José González, José M. García, José Duato
    Owner prediction for accelerating cache-to-cache transfer misses in a cc-NUMA architecture. [Citation Graph (0, 0)][DBLP]
    SC, 2002, pp:1-12 [Conf]
  28. José González, Antonio González
    Limits of Instruction Level Parallelism with Data Value Speculation. [Citation Graph (0, 0)][DBLP]
    VECPAR, 1998, pp:452-465 [Conf]
  29. José González, Fernando Latorre, Antonio González
    Cache organizations for clustered microarchitectures. [Citation Graph (0, 0)][DBLP]
    WMPI, 2004, pp:46-55 [Conf]
  30. Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals
    Dynamic Register Renaming Through Virtual-Physical Registers. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2000, v:2, n:, pp:- [Journal]
  31. Javier Cuenca, Domingo Giménez, José González
    Architecture of an automatically tuned linear algebra library. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 2004, v:30, n:2, pp:187-210 [Journal]
  32. Gregorio Bernabé, Ricardo Fernández, José M. García, Manuel E. Acacio, José González
    An efficient implementation of a 3D wavelet transform based encoder on hyper-threading technology. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 2007, v:33, n:1, pp:54-72 [Journal]
  33. José González, Antonio González
    Control-Flow Speculation through Value Prediction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:12, pp:1362-1376 [Journal]
  34. Teresa Monreal, Víctor Viñals, José González, Antonio González, Mateo Valero
    Late Allocation and Early Release of Physical Registers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:10, pp:1244-1259 [Journal]
  35. Manuel E. Acacio, José González, José M. García, José Duato
    An Architecture for High-Performance Scalable Shared-Memory Multiprocessors Exploiting On-Chip Integration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2004, v:15, n:8, pp:755-768 [Journal]
  36. Manuel E. Acacio, José González, José M. García, José Duato
    A Two-Level Directory Architecture for Highly Scalable cc-NUMA Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2005, v:16, n:1, pp:67-79 [Journal]
  37. Michael F. P. O'Boyle, François Bodin, José González, Lucian N. Vintan
    Topic 4 High-Performance Architectures and Compilers. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2007, pp:235- [Conf]
  38. Pedro Chaparro, José González, Grigorios Magklis, Qiong Cai, Antonio González
    Understanding the Thermal Implications of Multi-Core Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2007, v:18, n:8, pp:1055-1065 [Journal]

  39. Distributed cooperative caching. [Citation Graph (, )][DBLP]


  40. Meeting points: using thread criticality to adapt multicore hardware to parallel regions. [Citation Graph (, )][DBLP]


  41. Power-Efficient Spilling Techniques for Chip Multiprocessors. [Citation Graph (, )][DBLP]


  42. A software-hardware hybrid steering mechanism for clustered microarchitectures. [Citation Graph (, )][DBLP]


  43. Efficient resources assignment schemes for clustered multithreaded processors. [Citation Graph (, )][DBLP]


  44. Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors. [Citation Graph (, )][DBLP]


  45. Thread fusion. [Citation Graph (, )][DBLP]


  46. Dynamic thermal management using thin-film thermoelectric cooling. [Citation Graph (, )][DBLP]


  47. Modeling the Behaviour of Linear Algebra Algorithms with Message-Passing. [Citation Graph (, )][DBLP]


  48. Playability as Extension of Quality in Use in Video Games. [Citation Graph (, )][DBLP]


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