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Basilio B. Fraguela: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Basilio B. Fraguela, Ramon Doallo, Emilio L. Zapata
    Automatic Analytical Modeling for the Estimation of Cache Misses. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1999, pp:221-231 [Conf]
  2. Diego Andrade, Basilio B. Fraguela, Ramon Doallo
    Modeling the Cache Behavior of Codes with Arbitrary Data-Dependent Conditional Structures. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2004, pp:44-57 [Conf]
  3. José Luis Freire, Basilio B. Fraguela, Víctor M. Gulías
    Extending CAML Light to Perform Distributed Computation. [Citation Graph (0, 0)][DBLP]
    GULP-PRODE, 1995, pp:113-124 [Conf]
  4. Ramon Doallo, Basilio B. Fraguela, Emilio L. Zapata
    Cache Probabilistic Modeling for Basic Sparse Algebra Kernels Involving Matrices with a Non Uniform Distribution. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10345-0 [Conf]
  5. Ramon Doallo, Basilio B. Fraguela, Emilio L. Zapata
    Set Associative Cache Behavior Optimization. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1999, pp:229-238 [Conf]
  6. Basilio B. Fraguela, Ramon Doallo, Emilio L. Zapata
    Cache Misses Prediction for High Performance Sparse Algorithms. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1998, pp:224-233 [Conf]
  7. Ramon Doallo, Basilio B. Fraguela, Juan Touriño, Emilio L. Zapata
    Parallel Sparse Modified Gram-Schmidt QR Decomposition. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 1996, pp:646-653 [Conf]
  8. Jia Guo, Ganesh Bikshandi, Daniel Hoeflinger, Gheorghe Almási, Basilio B. Fraguela, María Jesús Garzarán, David A. Padua, Christoph von Praun
    Hierarchically tiled arrays for parallelism and locality. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  9. George Almási, Luiz De Rose, Basilio B. Fraguela, José E. Moreira, David A. Padua
    Programming for Locality and Parallelism with Hierarchically Tiled Arrays. [Citation Graph (0, 0)][DBLP]
    LCPC, 2003, pp:162-176 [Conf]
  10. Ganesh Bikshandi, Basilio B. Fraguela, Jia Guo, María Jesús Garzarán, Gheorghe Almási, José E. Moreira, David A. Padua
    Implementation of Parallel Numerical Algorithms Using Hierarchically Tiled Arrays. [Citation Graph (0, 0)][DBLP]
    LCPC, 2004, pp:87-101 [Conf]
  11. Basilio B. Fraguela, M. G. Carmueja, Diego Andrade
    Optimal Tile Size Selection Guided by Analytical Models. [Citation Graph (0, 0)][DBLP]
    PARCO, 2005, pp:565-572 [Conf]
  12. Ganesh Bikshandi, Jia Guo, Daniel Hoeflinger, Gheorghe Almási, Basilio B. Fraguela, María Jesús Garzarán, David A. Padua, Christoph von Praun
    Programming for parallelism and locality with hierarchically tiled arrays. [Citation Graph (0, 0)][DBLP]
    PPOPP, 2006, pp:48-57 [Conf]
  13. Basilio B. Fraguela, Jose Renau, Paul Feautrier, David A. Padua, Josep Torrellas
    Programming the FlexRAM parallel intelligent memory system. [Citation Graph (0, 0)][DBLP]
    PPOPP, 2003, pp:49-60 [Conf]
  14. Diego Andrade, Basilio B. Fraguela, Ramon Doallo
    Cache Behavior Modeling of Codes with Data-Dependent Conditionals. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:373-387 [Conf]
  15. Basilio B. Fraguela, Ramon Doallo, Emilio L. Zapata
    Modeling Set Associative Caches Behavior for Irregular Computations. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 1998, pp:192-201 [Conf]
  16. Diego Andrade, Basilio B. Fraguela, Ramon Doallo
    Analytical modeling of codes with arbitrary data-dependent conditional structures. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2006, v:52, n:7, pp:394-410 [Journal]
  17. Basilio B. Fraguela, Ramon Doallo, Juan Touriño, Emilio L. Zapata
    A compiler tool to predict memory hierarchy performance of scientific codes. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 2004, v:30, n:2, pp:225-248 [Journal]
  18. Basilio B. Fraguela, Ramon Doallo, Emilio L. Zapata
    Memory Hierarchy Performance Prediction for Blocked Sparse Algorithms. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1999, v:9, n:3, pp:347-360 [Journal]
  19. Basilio B. Fraguela, Ramon Doallo, Emilio L. Zapata
    Probabilistic Miss Equations: Evaluating Memory Hierarchy Performance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:3, pp:321-336 [Journal]
  20. Diego Andrade, Basilio B. Fraguela, Ramon Doallo
    Cache Behavior Modelling for Codes Involving Banded Matrices. [Citation Graph (0, 0)][DBLP]
    LCPC, 2006, pp:205-219 [Conf]
  21. Ganesh Bikshandi, Jia Guo, Christoph von Praun, Gabriel Tanase, Basilio B. Fraguela, María Jesús Garzarán, David A. Padua, Lawrence Rauchwerger
    Design and Use of htalib - A Library for Hierarchically Tiled Arrays. [Citation Graph (0, 0)][DBLP]
    LCPC, 2006, pp:17-32 [Conf]
  22. Diego Andrade, Basilio B. Fraguela, Ramon Doallo
    Precise automatable analytical modeling of the cache behavior of codes with indirections. [Citation Graph (0, 0)][DBLP]
    TACO, 2007, v:4, n:3, pp:- [Journal]

  23. Automatic Tuning of Discrete Fourier Transforms Driven by Analytical Modeling. [Citation Graph (, )][DBLP]


  24. Performance Evaluation of Unified Parallel C Collective Communications. [Citation Graph (, )][DBLP]


  25. A Generic Algorithm Template for Divide-and-Conquer in Multicore Systems. [Citation Graph (, )][DBLP]


  26. Adaptive line placement with the set balancing cache. [Citation Graph (, )][DBLP]


  27. Task-Parallel versus Data-Parallel Library-Based Programming in Multicore Systems. [Citation Graph (, )][DBLP]


  28. Programming with tiles. [Citation Graph (, )][DBLP]


  29. Performance Evaluation of MPI, UPC and OpenMP on Multicore Architectures. [Citation Graph (, )][DBLP]


  30. Static Prediction of Worst-Case Data Cache Performance in the Absence of Base Address Information. [Citation Graph (, )][DBLP]


  31. Design Issues in Parallel Array Languages for Shared Memory. [Citation Graph (, )][DBLP]


  32. Automated and accurate cache behavior analysis for codes with irregular access patterns. [Citation Graph (, )][DBLP]


  33. Special Issue: Current Trends in Compilers for Parallel Computers. [Citation Graph (, )][DBLP]


  34. Writing productive stencil codes with overlapped tiling. [Citation Graph (, )][DBLP]


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