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F. Jesús Sánchez: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Alex Aletà, Josep M. Codina, F. Jesús Sánchez, Antonio González, David R. Kaeli
    Exploiting Pseudo-Schedules to Guide Data Dependence Graph Partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2002, pp:281-290 [Conf]
  2. Enric Gibert, Jaume Abella, F. Jesús Sánchez, Xavier Vera, Antonio González
    Variable-Based Multi-module Data Caches for Clustered VLIW Processors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2005, pp:207-217 [Conf]
  3. Josep M. Codina, F. Jesús Sánchez, Antonio González
    A Unified Modulo Scheduling and Register Allocation Technique for Clustered Processors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:175-184 [Conf]
  4. F. Jesús Sánchez, Antonio González
    Fast, Accurate and Flexible Data Locality Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1998, pp:124-129 [Conf]
  5. F. Jesús Sánchez, Antonio González, Mateo Valero
    Static Locality Analysis for Cache Management. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1997, pp:261-271 [Conf]
  6. Enric Gibert, F. Jesús Sánchez, Antonio González
    Local Scheduling Techniques for Memory Coherence in a Clustered VLIW Processor with a Distributed Data Cache. [Citation Graph (0, 0)][DBLP]
    CGO, 2003, pp:193-203 [Conf]
  7. Josep M. Codina, F. Jesús Sánchez, Antonio González
    Virtual Cluster Scheduling Through the Scheduling Graph. [Citation Graph (0, 0)][DBLP]
    CGO, 2007, pp:89-101 [Conf]
  8. F. Jesús Sánchez, Antonio González
    The Effectiveness of Loop Unrolling for Modulo Scheduling in Clustered VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    ICPP, 2000, pp:555-0 [Conf]
  9. Enric Gibert, F. Jesús Sánchez, Antonio González
    An interleaved cache clustered VLIW processor. [Citation Graph (0, 0)][DBLP]
    ICS, 2002, pp:210-219 [Conf]
  10. F. Jesús Sánchez, Antonio González
    A locality sensitive multi-module cache with explicit management. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:51-59 [Conf]
  11. F. Jesús Sánchez, Antonio González
    Instruction Scheduling for Clustered VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:41-46 [Conf]
  12. Alex Aletà, Josep M. Codina, F. Jesús Sánchez, Antonio González
    Graph-partitioning based instruction scheduling for clustered processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:150-159 [Conf]
  13. Enric Gibert, F. Jesús Sánchez, Antonio González
    Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:123-133 [Conf]
  14. Enric Gibert, F. Jesús Sánchez, Antonio González
    Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:315-325 [Conf]
  15. F. Jesús Sánchez, Antonio González
    Modulo scheduling for a fully-distributed clustered VLIW architecture. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:124-133 [Conf]
  16. F. Jesús Sánchez, Antonio González
    Cache Sensitive Modulo Scheduling. [Citation Graph (0, 0)][DBLP]
    MICRO, 1997, pp:338-348 [Conf]
  17. Carlos Madriles, Carlos García Quiñones, F. Jesús Sánchez, Pedro Marcuello, Antonio González
    The Mitosis Speculative Multithreaded Architectures. [Citation Graph (0, 0)][DBLP]
    PARCO, 2005, pp:27-40 [Conf]
  18. Carlos García Quiñones, Carlos Madriles, F. Jesús Sánchez, Pedro Marcuello, Antonio González, Dean M. Tullsen
    Mitosis compiler: an infrastructure for speculative threading based on pre-computation slices. [Citation Graph (0, 0)][DBLP]
    PLDI, 2005, pp:269-279 [Conf]
  19. Enric Gibert, F. Jesús Sánchez, Antonio González
    Instruction scheduling for a clustered VLIW processor with a word-interleaved cache. [Citation Graph (0, 0)][DBLP]
    Concurrency and Computation: Practice and Experience, 2006, v:18, n:11, pp:1391-1411 [Journal]
  20. F. Jesús Sánchez, Antonio González
    Clustered Modulo Scheduling in a VLIW Architecture with Distributed Cache . [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2001, v:3, n:, pp:- [Journal]
  21. F. Jesús Sánchez, Antonio González
    Software Data Prefetching for Software Pipelined Loops. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1999, v:58, n:2, pp:236-259 [Journal]
  22. F. Jesús Sánchez, Antonio González
    Analyzing Data Locality in Numeric Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2000, v:20, n:4, pp:58-66 [Journal]
  23. Enric Gibert, F. Jesús Sánchez, Antonio González
    Distributed Data Cache Designs for Clustered VLIW Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:10, pp:1227-1241 [Journal]

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