Search the dblp DataBase
David R. Kaeli :
[Publications ]
[Author Rank by year ]
[Co-authors ]
[Prefers ]
[Cites ]
[Cited by ]
Publications of Author
Alex Aletà , Josep M. Codina , F. Jesús Sánchez , Antonio González , David R. Kaeli Exploiting Pseudo-Schedules to Guide Data Dependence Graph Partitioning. [Citation Graph (0, 0)][DBLP ] IEEE PACT, 2002, pp:281-290 [Conf ] Jason P. Casmira , John Fraser , David R. Kaeli , Waleed Meleis Operating System Impact on Trace-Driven Simulation. [Citation Graph (0, 0)][DBLP ] Annual Simulation Symposium, 1998, pp:76-82 [Conf ] Suleyman Sair , Guiseppe Olivadoti , David R. Kaeli , José Fridman DSPTune: A Performance Evaluation Toolset for the SHARC Signal Processor. [Citation Graph (0, 0)][DBLP ] Annual Simulation Symposium, 2000, pp:51-57 [Conf ] Angela Sampogna , David R. Kaeli , Daniel Green , Michael Silva , Christopher J. Sniezek Performance Modeling Using Object-Oriented Execution-Driven Simulation. [Citation Graph (0, 0)][DBLP ] Annual Simulation Symposium, 1996, pp:183-192 [Conf ] Micha Moffie , Winnie Cheng , David R. Kaeli , Qin Zhao Hunting Trojan Horses. [Citation Graph (0, 0)][DBLP ] ASID, 2006, pp:12-17 [Conf ] Salvador Petit , Julio Sahuquillo , Jose M. Such , David R. Kaeli Exploiting temporal locality in drowsy cache policies. [Citation Graph (0, 0)][DBLP ] Conf. Computing Frontiers, 2005, pp:371-377 [Conf ] Alex Aletà , Josep M. Codina , Antonio González , David R. Kaeli Heterogeneous Clustered VLIW Microarchitectures. [Citation Graph (0, 0)][DBLP ] CGO, 2007, pp:354-366 [Conf ] Hossein Asadi , Vilas Sridharan , Mehdi Baradaran Tahoori , David R. Kaeli Vulnerability analysis of L2 cache elements to single event upsets. [Citation Graph (0, 0)][DBLP ] DATE, 2006, pp:1276-1281 [Conf ] Augustus K. Uht , Alireza Khalafi , David Morano , Marcos de Alba , David R. Kaeli Realizing High IPC Using Time-Tagged Resource-Flow Computing. [Citation Graph (0, 0)][DBLP ] Euro-Par, 2002, pp:490-499 [Conf ] Ke Ning , David R. Kaeli Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems. [Citation Graph (0, 0)][DBLP ] HiPEAC, 2005, pp:87-101 [Conf ] David R. Kaeli , Bruce Jacobs Fifth Annual Workshop on Computer Education. [Citation Graph (0, 0)][DBLP ] HPCA, 1999, pp:320- [Conf ] John Kalamatianos , David R. Kaeli Temporal-Based Procedure Reordering for Improved Instruction Cache Performance. [Citation Graph (0, 0)][DBLP ] HPCA, 1998, pp:244-253 [Conf ] Yue Liu , David R. Kaeli Branch-Directed and Stride-Based Data Cache Prefetching. [Citation Graph (0, 0)][DBLP ] ICCD, 1996, pp:225-230 [Conf ] Juemin Zhang , Waleed Meleis , David R. Kaeli , Tao Wu Acceleration of Maximum Likelihood Estimation for Tomosynthesis Mammography. [Citation Graph (0, 0)][DBLP ] ICPADS (1), 2006, pp:291-299 [Conf ] Yijian Wang , David R. Kaeli Profile-guided I/O partitioning. [Citation Graph (0, 0)][DBLP ] ICS, 2003, pp:252-260 [Conf ] Jennifer Black , Emanuel Melachrinoudis , David R. Kaeli Bi-Criteria Models for All-Uses Test Suite Reduction. [Citation Graph (0, 0)][DBLP ] ICSE, 2004, pp:106-115 [Conf ] Morteza Fayyazi , David R. Kaeli , Waleed Meleis Parallel Maximum Weight Bipartite Matching Algorithms for Scheduling in Input-Queued Switches. [Citation Graph (0, 0)][DBLP ] IPDPS, 2004, pp:- [Conf ] David R. Kaeli , Philip G. Emma Branch History Table Prediction of Moving Target Branches due to Subroutine Returns. [Citation Graph (0, 0)][DBLP ] ISCA, 1991, pp:34-42 [Conf ] Kaushal Sanghai , Ting Su , Jennifer G. Dy , David R. Kaeli A multinomial clustering model for fast simulation of computer architecture designs. [Citation Graph (0, 0)][DBLP ] KDD, 2005, pp:808-813 [Conf ] Mark S. Squillante , David R. Kaeli , Himanshu Sinh Analytic Models of Workload Behavior and Pipeline Performance. [Citation Graph (0, 0)][DBLP ] MASCOTS, 1997, pp:91-0 [Conf ] Yijian Wang , David R. Kaeli Execution-Driven Simulation of Network Storage Systems. [Citation Graph (0, 0)][DBLP ] MASCOTS, 2004, pp:604-611 [Conf ] Alex Aletà , Josep M. Codina , Antonio González , David R. Kaeli Instruction Replication for Clustered Microarchitectures. [Citation Graph (0, 0)][DBLP ] MICRO, 2003, pp:326-338 [Conf ] John Kalamatianos , David R. Kaeli Predicting Indirect Branches via Data Compression. [Citation Graph (0, 0)][DBLP ] MICRO, 1998, pp:272-281 [Conf ] Ke Ning , David R. Kaeli Bus Power Estimation and Power-Efficient Bus Arbitration for System-on-a-Chip Embedded Systems. [Citation Graph (0, 0)][DBLP ] PACS, 2004, pp:95-106 [Conf ] S. Belayneh , H. Sinha , David R. Kaeli Improving Multiprocessor Scalability Using Lockup Free Caches. [Citation Graph (0, 0)][DBLP ] PDPTA, 1996, pp:619-622 [Conf ] Morteza Fayyazi , David R. Kaeli Localized Message Passing Structure for High Speed Ethernet Packet Switching. [Citation Graph (0, 0)][DBLP ] PDPTA, 2002, pp:1551-1557 [Conf ] Morteza Fayyazi , David R. Kaeli , Zainalabedin Navabi Dynamic Input Buffer Allocation (DIBA) for Fault Tolerant Ethernet Packet Switching. [Citation Graph (0, 0)][DBLP ] PDPTA, 2003, pp:819-823 [Conf ] Alex Aletà , Josep M. Codina , Antonio González , David R. Kaeli Demystifying on-the-fly spill code. [Citation Graph (0, 0)][DBLP ] PLDI, 2005, pp:180-189 [Conf ] Amir H. Hashemi , David R. Kaeli , Brad Calder Efficient Procedure Mapping Using Cache Line Coloring. [Citation Graph (0, 0)][DBLP ] PLDI, 1997, pp:171-182 [Conf ] Deniz Balkan , John Kalamatianos , David R. Kaeli A Study of Errant Pipeline Flushes Caused by Value Misspeculation. [Citation Graph (0, 0)][DBLP ] SBAC-PAD, 2004, pp:32-39 [Conf ] Salvador Petit , Julio Sahuquillo , Ana Pont , David R. Kaeli Characterizing the Dynamic Behavior of Workload Execution in SVM systems. [Citation Graph (0, 0)][DBLP ] SBAC-PAD, 2004, pp:230-237 [Conf ] David R. Kaeli PC Workload Characterization. [Citation Graph (0, 0)][DBLP ] SIGMETRICS, 1989, pp:220- [Conf ] David R. Kaeli Issues in Trace-Driven Simulation. [Citation Graph (0, 0)][DBLP ] Performance/SIGMETRICS Tutorials, 1993, pp:224-244 [Conf ] Huanmei Wu , Betty Salzberg , Gregory C. Sharp , Steve B. Jiang , Hiroki Shirato , David R. Kaeli Subsequence Matching on Structured Time Series Data. [Citation Graph (0, 0)][DBLP ] SIGMOD Conference, 2005, pp:682-693 [Conf ] Zoran Mijanic , David R. Kaeli A Study of 80X86/80X87 Floating-Point Execution. [Citation Graph (0, 0)][DBLP ] SIGSMALL/PC, 1991, pp:28-32 [Conf ] Huanmei Wu , Becky Norum , Judith Newmark , Betty Salzberg , Carol M. Warner , Charles DiMarzio , David R. Kaeli The CenSSIS Image Database. [Citation Graph (0, 0)][DBLP ] SSDBM, 2003, pp:117-126 [Conf ] Brian Mullins , Hossein Asadi , Mehdi Baradaran Tahoori , David R. Kaeli , Kevin Granlund , Rudy Bauer , Scott Romano Case Study: Soft Error Rate Analysis in Storage Systems. [Citation Graph (0, 0)][DBLP ] VTS, 2007, pp:256-264 [Conf ] Erik R. Altman , David R. Kaeli , Yaron Sheffer Welcome to the Opportunities of Binary Translation. [Citation Graph (0, 0)][DBLP ] IEEE Computer, 2000, v:33, n:3, pp:40-45 [Journal ] Jason P. Casmira , David P. Hunter , David R. Kaeli Tracing and Characterization of Windows NT-based System Workloads. [Citation Graph (0, 0)][DBLP ] Digital Technical Journal, 1998, v:10, n:1, pp:6-21 [Journal ] David R. Kaeli , O. Richard LaMaire , Peter P. Hennet , William W. White , William J. Starke Real-Time Trace Generation. [Citation Graph (0, 0)][DBLP ] Int. Journal in Computer Simulation, 1996, v:6, n:1, pp:53-0 [Journal ] Stephen Strickland , Erhan Ergin , David R. Kaeli , Paul M. Zavracky VLSI design in the 3rd dimension. [Citation Graph (0, 0)][DBLP ] Integration, 1998, v:25, n:1, pp:1-16 [Journal ] Morteza Fayyazi , David R. Kaeli , Waleed Meleis An adjustable linear time parallel algorithm for maximum weight bipartite matching. [Citation Graph (0, 0)][DBLP ] Inf. Process. Lett., 2006, v:97, n:5, pp:186-190 [Journal ] John Kalamatianos , David R. Kaeli Indirect Branch Prediction Using Data Compression Techniques. [Citation Graph (0, 0)][DBLP ] J. Instruction-Level Parallelism, 1999, v:1, n:, pp:- [Journal ] Augustus K. Uht , David Morano , Alireza Khalafi , David R. Kaeli Levo - A Scalable Processor With High IPC. [Citation Graph (0, 0)][DBLP ] J. Instruction-Level Parallelism, 2003, v:5, n:, pp:- [Journal ] David Morano , Alireza Khalafi , David R. Kaeli , Augustus K. Uht Realizing high IPC through a scalable memory-latency tolerant multipath microarchitecture. [Citation Graph (0, 0)][DBLP ] SIGARCH Computer Architecture News, 2003, v:31, n:1, pp:16-25 [Journal ] Erik R. Altman , David R. Kaeli WBT-2000: workshop on binary translation - 2000. [Citation Graph (0, 0)][DBLP ] SIGARCH Computer Architecture News, 2001, v:29, n:1, pp:23-25 [Journal ] Erik R. Altman , David R. Kaeli Workshop on binary translation - 2001. [Citation Graph (0, 0)][DBLP ] SIGARCH Computer Architecture News, 2001, v:29, n:5, pp:84-85 [Journal ] Derek Uluski , Micha Moffie , David R. Kaeli Characterizing antivirus workload execution. [Citation Graph (0, 0)][DBLP ] SIGARCH Computer Architecture News, 2005, v:33, n:1, pp:90-98 [Journal ] Dong Ye , David R. Kaeli A reliable return address stack: microarchitectural features to defeat stack smashing. [Citation Graph (0, 0)][DBLP ] SIGARCH Computer Architecture News, 2005, v:33, n:1, pp:73-80 [Journal ] Alex Aletà , Josep M. Codina , Antonio González , David R. Kaeli Removing communications in clustered microarchitectures through instruction replication. [Citation Graph (0, 0)][DBLP ] TACO, 2004, v:1, n:2, pp:127-151 [Journal ] Haldun Hadimioglu , David R. Kaeli , Fabrizio Lombardi Introduction to the Special Section on High Performance Memory Systems. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 2001, v:50, n:11, pp:1103-1104 [Journal ] David R. Kaeli , Philip G. Emma Improving the Accuracy of History Based Branch Prediction. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1997, v:46, n:4, pp:469-472 [Journal ] John Kalamatianos , Alireza Khalafi , David R. Kaeli , Waleed Meleis Analysis of Temporal-Based Program Behavior for Improved Instruction Cache Performance. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1999, v:48, n:2, pp:168-175 [Journal ] Vilas Sridharan , Hossein Asadi , Mehdi Baradaran Tahoori , David R. Kaeli Reducing Data Cache Susceptibility to Soft Errors. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Dependable Sec. Comput., 2006, v:3, n:4, pp:353-364 [Journal ] Salvador Petit , Julio Sahuquillo , Ana Pont , David R. Kaeli Addressing a workload characterization study to the design of consistency protocols. [Citation Graph (0, 0)][DBLP ] The Journal of Supercomputing, 2006, v:38, n:1, pp:49-72 [Journal ] Ke Ning , David R. Kaeli External memory page remapping for embedded multimedia systems. [Citation Graph (0, 0)][DBLP ] LCTES, 2007, pp:185-194 [Conf ] Michael G. Benjamin , David R. Kaeli Stream Image Processing on a Dual-Core Embedded System. [Citation Graph (0, 0)][DBLP ] SAMOS, 2007, pp:149-158 [Conf ] Dong Ye , Joydeep Ray , Christophe Harle , David R. Kaeli Performance Characterization of SPEC CPU2006 Integer Benchmarks on x86-64 Architecture. [Citation Graph (0, 0)][DBLP ] IISWC, 2006, pp:120-127 [Conf ] Accelerating phase unwrapping and affine transformations for optical quadrature microscopy using CUDA. [Citation Graph (, )][DBLP ] Architecture-aware optimization targeting multithreaded stream computing. [Citation Graph (, )][DBLP ] Accelerating the local outlier factor algorithm on a GPU for intrusion detection systems. [Citation Graph (, )][DBLP ] Load Balancing using Grid-based Peer-to-Peer Parallel I/O. [Citation Graph (, )][DBLP ] Applying Spectral Analysis to Identify Individual Application Signatures. [Citation Graph (, )][DBLP ] Eliminating microarchitectural dependency from Architectural Vulnerability. [Citation Graph (, )][DBLP ] Exploring the multiple-GPU design space. [Citation Graph (, )][DBLP ] Multi GPU Implementation of Iterative Tomographic Reconstruction Algorithms. [Citation Graph (, )][DBLP ] Profile-Guided Optimization of Critical Medical Imaging Algorithms. [Citation Graph (, )][DBLP ] Using hardware vulnerability factors to enhance AVF analysis. [Citation Graph (, )][DBLP ] Balancing Performance and Reliability in the Memory Hierarchy. [Citation Graph (, )][DBLP ] Software transactional memory for multicore embedded systems. [Citation Graph (, )][DBLP ] Scalable Performance on a Distributed Shared-Memory Machine. [Citation Graph (, )][DBLP ] Data transformations enabling loop vectorization on multithreaded data parallel architectures. [Citation Graph (, )][DBLP ] Exploring Novel Parallelization Technologies for 3-D Imaging Applications. [Citation Graph (, )][DBLP ] Quantifying load imbalance on virtualized enterprise servers. [Citation Graph (, )][DBLP ] Archer: A Community Distributed Computing Infrastructure for Computer Architecture Research and Education. [Citation Graph (, )][DBLP ] Interactive Deformable Registration Visualization and Analysis of 4D Computed Tomography. [Citation Graph (, )][DBLP ] Experiences with the Blackfin architecture in an embedded systems lab. [Citation Graph (, )][DBLP ] Archer: A Community Distributed Computing Infrastructure for Computer Architecture Research and Education [Citation Graph (, )][DBLP ] Search in 0.010secs, Finished in 0.016secs