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Title:
Author:
Arvind: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Arvind, Rishiyur S. Nikhil, Keshav Pingali
    I-Structures: Data Structures for Parallel Computing. [Citation Graph (2, 0)][DBLP]
    ACM Trans. Program. Lang. Syst., 1989, v:11, n:4, pp:598-632 [Journal]
  2. Arvind, Rishiyur S. Nikhil
    Executing a Program on the MIT Tagged-Token Dataflow Architecture. [Citation Graph (1, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:3, pp:300-318 [Journal]
  3. Boon Seong Ang, Derek Chiou, Larry Rudolph, Arvind
    The StarT-Voyager Parallel System. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1998, pp:185-0 [Conf]
  4. Daniel L. Rosenband, Arvind
    Modular scheduling of guarded atomic actions. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:55-60 [Conf]
  5. Arvind, Robert A. Iannucci
    Two Fundamental Issues in Multiprocessing. [Citation Graph (0, 0)][DBLP]
    Parallel Computing in Science and Engineering, 1987, pp:61-88 [Conf]
  6. Derek Chiou, Boon Seong Ang, Robert Greiner, Arvind, James C. Hoe, Michael J. Beckerle, James E. Hicks, G. Andrew Boughton
    START-NG: Delivering Seamless Parallel Computing. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1995, pp:101-116 [Conf]
  7. Joseph E. Stoy, Xiaowei Shen, Arvind
    Proofs of Correctness of Cache-Coherence Protocols. [Citation Graph (0, 0)][DBLP]
    FME, 2001, pp:43-71 [Conf]
  8. Shail Aditya, Arvind, Joseph E. Stoy
    Semantics of Barriers in a Non-Strict, Implicitly-Parallel Language. [Citation Graph (0, 0)][DBLP]
    FPCA, 1995, pp:204-215 [Conf]
  9. Zena M. Ariola, Arvind
    P-TAC: A Parallel Intermediate Language. [Citation Graph (0, 0)][DBLP]
    FPCA, 1989, pp:230-242 [Conf]
  10. Paul S. Barth, Rishiyur S. Nikhil, Arvind
    M-Structures: Extending a Parallel, Non-strict, Functional Language with State. [Citation Graph (0, 0)][DBLP]
    FPCA, 1991, pp:538-568 [Conf]
  11. Arvind
    Demand-Driven Evaluation on Dataflow Machine. [Citation Graph (0, 0)][DBLP]
    FSTTCS, 1985, pp:411- [Conf]
  12. Arvind, Jan-Willem Maessen, Rishiyur S. Nikhil, Joseph E. Stoy
    A Lambda Calculus with Letrecs and Barriers. [Citation Graph (0, 0)][DBLP]
    FSTTCS, 1996, pp:19-36 [Conf]
  13. Arvind, Rishiyur S. Nikhil, Keshav Pingali
    I-structures: Data structures for parallel computing. [Citation Graph (0, 0)][DBLP]
    Graph Reduction, 1986, pp:336-369 [Conf]
  14. Arvind
    Rethinking Computer Architecture Research. [Citation Graph (0, 0)][DBLP]
    HiPC, 2004, pp:1-2 [Conf]
  15. Arvind, J. Dean Brock
    Streams and Managers. [Citation Graph (0, 0)][DBLP]
    Operating Systems Engineering, 1980, pp:452-465 [Conf]
  16. Arvind, Rishiyur S. Nikhil, Daniel L. Rosenband, Nirav Dave
    High-level synthesis: an essential ingredient for designing complex ASICs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:775-782 [Conf]
  17. James C. Hoe, Arvind
    Synthesis of Operation-Centric Hardware Descriptions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:511-518 [Conf]
  18. Arvind, Kattamuri Ekanadham
    Future Scientific Programming on Parallel Machines. [Citation Graph (0, 0)][DBLP]
    ICS, 1987, pp:639-686 [Conf]
  19. Xiaowei Shen, Arvind, Larry Rudolph
    CACHET: an adaptive cache coherence protocol for distributed shared-memory systems. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:135-144 [Conf]
  20. Arvind, Kim P. Gostelow
    A Computer Capable of Exchanging Processors for Time. [Citation Graph (0, 0)][DBLP]
    IFIP Congress, 1977, pp:849-853 [Conf]
  21. James C. Hoe, Arvind
    Hardware Synthesis from Term Rewriting Systems. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:595-619 [Conf]
  22. Hari Balakrishnan, Srinivas Devadas, Douglas Ehlert, Arvind
    Rate Guarantees and Overload Protection in Input-Queued Switches. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 2004, pp:- [Conf]
  23. Boon Seong Ang, Derek Chiou, Larry Rudolph, Arvind
    Micro-Architectures of High Performance, Multi-User System Area Network Interface Cards. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2000, pp:13-20 [Conf]
  24. Arvind
    Prospects of ubiquitous parallel computing. [Citation Graph (0, 0)][DBLP]
    IPPS, 1994, pp:2-3 [Conf]
  25. Ryan Newton, Arvind, Matt Welsh
    Building up to macroprogramming: an intermediate language for sensor networks. [Citation Graph (0, 0)][DBLP]
    IPSN, 2005, pp:37-44 [Conf]
  26. Arvind
    Data Flow Languages and Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 1981, pp:1- [Conf]
  27. Arvind, Robert A. Iannucci
    A Critique of Multiprocessing von Neumann Style [Citation Graph (0, 0)][DBLP]
    ISCA, 1983, pp:426-436 [Conf]
  28. Arvind, Jan-Willem Maessen
    Memory Model = Instruction Reordering + Store Atomicity. [Citation Graph (0, 0)][DBLP]
    ISCA, 2006, pp:29-40 [Conf]
  29. David E. Culler, Arvind
    Resource Requirements of Dataflow Programs. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:141-150 [Conf]
  30. Rishiyur S. Nikhil, G. M. Papadopoulos, Arvind
    *T: A Multithreaded Massively Parallel Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 1992, pp:156-167 [Conf]
  31. Xiaowei Shen, Arvind, Larry Rudolph
    Commit-Reconcile & Fences (CRF): A New Memory Model for Architects and Compiler Writers. [Citation Graph (0, 0)][DBLP]
    ISCA, 1999, pp:150-161 [Conf]
  32. Zena M. Ariola, Arvind
    Compilation of Id. [Citation Graph (0, 0)][DBLP]
    LCPC, 1991, pp:99-121 [Conf]
  33. Arvind, Alejandro Caro, Jan-Willem Maessen, Shail Aditya
    A Multithreaded Substrate and Compilation Model for the Implicity Parallel Language pH. [Citation Graph (0, 0)][DBLP]
    LCPC, 1996, pp:519-533 [Conf]
  34. Arvind
    Bluespec: A language for hardware design, simulation, synthesis and verification Invited Talk. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2003, pp:249-0 [Conf]
  35. Nirav Dave, Man Cheuk Ng, Arvind
    Automatic synthesis of cache-coherence protocol processors using Bluespec. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2005, pp:25-34 [Conf]
  36. Jan-Willem Maessen, Arvind, Xiaowei Shen
    Improving the Java memory model using CRF. [Citation Graph (0, 0)][DBLP]
    OOPSLA, 2000, pp:1-12 [Conf]
  37. Arvind, Rishiyur S. Nikhil
    Executing a Program on the MIT Tagged-Token Dataflow Architecture. [Citation Graph (0, 0)][DBLP]
    PARLE (2), 1987, pp:1-29 [Conf]
  38. Zena M. Ariola, Arvind
    A Syntactic Approach to Program Transformations. [Citation Graph (0, 0)][DBLP]
    PEPM, 1991, pp:116-129 [Conf]
  39. Arvind, Kim P. Gostelow, Wil Plouffe
    Indeterminancy, Monitors, and Dataflow. [Citation Graph (0, 0)][DBLP]
    SOSP, 1977, pp:159-169 [Conf]
  40. Arvind, Richard Y. Kain, E. Sadeh
    On Reference String Generation Processes. [Citation Graph (0, 0)][DBLP]
    SOSP, 1973, pp:80-87 [Conf]
  41. Arvind
    UNUM: A Tinker-Toy Approach to Building Multicore PowerPC Microarchitectures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:39- [Conf]
  42. Arvind, Kim P. Gostelow
    The U-Interpreter. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1982, v:15, n:2, pp:42-49 [Journal]
  43. Tilak Agerwala, Arvind
    Data Flow Systems - Guest Editors' Introduction. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1982, v:15, n:2, pp:10-13 [Journal]
  44. Arvind, Jan-Willem Maessen, Rishiyur S. Nikhil, Joseph E. Stoy
    LambdaS: an implicitly parallel lambda-calculus with letrec, synchronization and side-effects. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 1998, v:16, n:3, pp:- [Journal]
  45. Arvind, Kattamuri Ekanadham
    Future Scientific Programming on Parallel Machines. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1988, v:5, n:5, pp:460-493 [Journal]
  46. James E. Hicks, Derek Chiou, Boon Seong Ang, Arvind
    Performance Studies of Id on the Monsoon Dataflow System. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1993, v:18, n:3, pp:273-300 [Journal]
  47. Andrew Shaw, Arvind, Kyoo-Chan Cho, Christopher Hill, R. Paul Johnson, John Marshall
    A Comparison of Implicitly Parallel Multithreaded and Data-Parallel Implementations of an Ocean Model. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1998, v:48, n:1, pp:1-51 [Journal]
  48. Arvind, Anton T. Dahbura, Alejandro Caro
    From Monsoon to StarT-Voyager: University-Industry Collaboration. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2000, v:20, n:3, pp:75-84 [Journal]
  49. James C. Hoe, Arvind
    Operation-centric hardware description and synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:9, pp:1277-1288 [Journal]
  50. Zena M. Ariola, Arvind
    Properties of a First-Order Functional Language with Sharing. [Citation Graph (0, 0)][DBLP]
    Theor. Comput. Sci., 1995, v:146, n:1&2, pp:69-108 [Journal]
  51. Keshav Pingali, Arvind
    Efficient Demand-Driven Evaluation - Part 1. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Program. Lang. Syst., 1985, v:7, n:2, pp:311-333 [Journal]
  52. Keshav Pingali, Arvind
    Efficient Demand-Driven Evaluation - Part 2. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Program. Lang. Syst., 1986, v:8, n:1, pp:109-139 [Journal]
  53. Keshav Pingali, Arvind
    Clarification of ``Feeding Inputs on Demand'' in Efficient Demand-Driven Evaluation - Part 1. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Program. Lang. Syst., 1986, v:8, n:1, pp:140-141 [Journal]
  54. Nirav Dave, Michael Pellauer, S. Gerding, Arvind
    802.11a transmitter: a case study in microarchitectural exploration. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2006, pp:59-68 [Conf]
  55. Nirav Dave, Arvind, Michael Pellauer
    Scheduling as Rule Composition. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2007, pp:51-60 [Conf]
  56. Man Cheuk Ng, Muralidaran Vijayaraghavan, Nirav Dave, Arvind, Gopal Raghavan, Jamey Hicks
    From WiFi to WiMAX: Techniques for High-Level IP Reuse across Different OFDM Protocols. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2007, pp:71-80 [Conf]
  57. Jan-Willem Maessen, Arvind
    Store Atomicity for Transactional Memory. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2007, v:174, n:9, pp:117-137 [Journal]

  58. Getting Formal Verification into Design Flow. [Citation Graph (, )][DBLP]


  59. A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs. [Citation Graph (, )][DBLP]


  60. Synthesis from multi-cycle atomic actions as a solution to the timing closure problem. [Citation Graph (, )][DBLP]


  61. Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs. [Citation Graph (, )][DBLP]


  62. H.264 Decoder: A Case Study in Multiple Design Points. [Citation Graph (, )][DBLP]


  63. Hands-on Introduction to Bluespec System Verilog (BSV) (Abstract). [Citation Graph (, )][DBLP]


  64. Advances in ESL Design. [Citation Graph (, )][DBLP]


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