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Robert D. Mullins: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. D. K. Arvind, Robert D. Mullins
    A Fully Asynchronous Superscalar Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1999, pp:17-22 [Conf]
  2. Robert D. Mullins, Andrew West, Simon W. Moore
    The design and implementation of a low-latency on-chip network. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:164-169 [Conf]
  3. D. K. Arvind, Robert D. Mullins, Vinod E. F. Rebello
    Micronets: a model for decentralising control in asynchronous processor architectures. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1995, pp:190-199 [Conf]
  4. George S. Taylor, Simon W. Moore, Robert D. Mullins, Peter Robinson
    Point to Point GALS Interconnect. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:69-75 [Conf]
  5. Simon W. Moore, Robert D. Mullins, Paul A. Cunningham, Ross J. Anderson, George S. Taylor
    Improving Smart Card Security Using Self-Timed Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:211-0 [Conf]
  6. Robert D. Mullins, Simon W. Moore
    Demystifying Data-Driven and Pausible Clocking Schemes. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2007, pp:175-185 [Conf]
  7. Jacques J. A. Fournier, Simon W. Moore, Huiyun Li, Robert D. Mullins, George S. Taylor
    Security Evaluation of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    CHES, 2003, pp:137-151 [Conf]
  8. Simon W. Moore, George S. Taylor, Paul A. Cunningham, Robert D. Mullins, Peter Robinson
    Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:73-0 [Conf]
  9. Robert D. Mullins, Andrew West, Simon W. Moore
    Low-Latency Virtual-Channel Routers for On-Chip Networks. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:188-197 [Conf]
  10. Simon W. Moore, Ross J. Anderson, Robert D. Mullins, George S. Taylor, Jacques J. A. Fournier
    Balanced self-checking asynchronous logic for smart card applications. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2003, v:27, n:9, pp:421-430 [Journal]
  11. Arnab Banerjee, Robert Mullins, Simon Moore
    A Power and Energy Exploration of Network-on-Chip Architectures. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:163-172 [Conf]

  12. A Network of Time-Division Multiplexed Wiring for FPGAs. [Citation Graph (, )][DBLP]


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