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Zhiyuan Li: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Zhiyuan Li
    Reducing Cache Conflicts by Partitioning and Privatizing Shared Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1999, pp:183-190 [Conf]
  2. Zhiyuan Li, Cheng Wang, Rong Xu
    Computation offloading to save energy on handheld devices: a partition scheme. [Citation Graph (0, 0)][DBLP]
    CASES, 2001, pp:238-246 [Conf]
  3. Yonghua Ding, Zhiyuan Li
    A Compiler Scheme for Reusing Intermediate Computation Results. [Citation Graph (0, 0)][DBLP]
    CGO, 2004, pp:279-290 [Conf]
  4. Zhiyuan Li, Junjie Gu, Gyungho Lee
    Interprocedural Analysis Based on Guarded Array Regions. [Citation Graph (0, 0)][DBLP]
    Compiler Optimizations for Scalable Parallel Systems Languages, 2001, pp:221-246 [Conf]
  5. Scott Hauck, Zhiyuan Li, Eric J. Schwabe
    Configuration Compression for the Xilinx XC6200 FPGA. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:138-146 [Conf]
  6. Zhiyuan Li, Katherine Compton, Scott Hauck
    Configuration Caching Management Techniques for Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:22-38 [Conf]
  7. Zhiyuan Li, Scott Hauck
    Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:187-195 [Conf]
  8. Zhiyuan Li, Scott Hauck
    Don't Care Discovery for FPGA Configuration Compression. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:91-98 [Conf]
  9. Zhiyuan Li, FengChang Lai, Mingyan Yu
    Low-noise high-precision operational amplifier using vertical NPN transistor in CMOS technology. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:123-126 [Conf]
  10. Yuldi Tirta, Zhiyuan Li, Yung-Hsiang Lu, Saurabh Bagchi
    Efficient Collection of Sensor Data in Remote Fields Using Mobile Collectors. [Citation Graph (0, 0)][DBLP]
    ICCCN, 2004, pp:515-520 [Conf]
  11. Rong Xu, Zhiyuan Li, Cheng Wang, Peifeng Ni
    Impact of Data Compression on Energy Consumption of Wireless-Networked Handheld Devices. [Citation Graph (0, 0)][DBLP]
    ICDCS, 2003, pp:302-311 [Conf]
  12. Sangyeun Cho, Jenn-Yuan Tsai, Yonghong Song, Bixia Zheng, Stephen J. Schwinn, Xin Wang, Qing Zhao, Zhiyuan Li, David J. Lilja, Pen-Chung Yew
    High-Level Information - An Approach for Integrating Front-End and Back-End Compilers. [Citation Graph (0, 0)][DBLP]
    ICPP, 1998, pp:346-355 [Conf]
  13. Rudolf Eigenmann, Jay Hoeflinger, Greg Jaxon, Zhiyuan Li, David A. Padua
    Restructuring Fortran Programs for Cedar. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1991, pp:57-66 [Conf]
  14. Zhiyuan Li, Trung N. Nguyen
    An Empirical Study of the Workload Distribution Under Static Scheduling. [Citation Graph (0, 0)][DBLP]
    ICPP, 1994, pp:259-263 [Conf]
  15. Zhiyuan Li, Pen-Chung Yew
    Interprocedural Analysis for Parallel Programs. [Citation Graph (0, 0)][DBLP]
    ICPP (2), 1988, pp:221-228 [Conf]
  16. Trung N. Nguyen, Zhiyuan Li, David J. Lilja
    Efficient Use of Dynamically Tagged Directories Through Compiler Analysis [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:112-119 [Conf]
  17. Zhiyu Shen, Zhiyuan Li, Pen-Chung Yew
    An Empirical Study on Array Subscripts and Data Dependencies. [Citation Graph (0, 0)][DBLP]
    ICPP (2), 1989, pp:145-152 [Conf]
  18. Yonghong Song, Zhiyuan Li
    Applying Array Contraction to a Sequence of DOALL Loops. [Citation Graph (0, 0)][DBLP]
    ICPP, 2004, pp:46-53 [Conf]
  19. Zhiyuan Li
    Compiler algorithms for event variable synchronization. [Citation Graph (0, 0)][DBLP]
    ICS, 1991, pp:85-95 [Conf]
  20. Zhiyuan Li
    Array privatization for parallel execution of loops. [Citation Graph (0, 0)][DBLP]
    ICS, 1992, pp:313-322 [Conf]
  21. Zhiyuan Li, Pen-Chung Yew, Chuan-Qi Zhu
    Data dependence analysis on multi-dimensional array references. [Citation Graph (0, 0)][DBLP]
    ICS, 1989, pp:215-224 [Conf]
  22. Farnaz Mounes-Toussi, David J. Lilja, Zhiyuan Li
    An evaluation of a compiler optimization for improving the performance of a coherence directory. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1994, pp:75-84 [Conf]
  23. Yonghong Song, Rong Xu, Cheng Wang, Zhiyuan Li
    Data locality enhancement by memory reduction. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:50-64 [Conf]
  24. Trung N. Nguyen, Farnaz Mounes-Toussi, David J. Lilja, Zhiyuan Li
    A Compiler-Assisted Scheme for Adaptive Cache Coherence Enforcement. [Citation Graph (0, 0)][DBLP]
    IFIP PACT, 1994, pp:69-78 [Conf]
  25. Shiwa S. Fu, Nian-Feng Tzeng, Zhiyuan Li
    Empirical Evaluation of Distributed Mutual Exclusion Algorithms. [Citation Graph (0, 0)][DBLP]
    IPPS, 1997, pp:255-259 [Conf]
  26. Zhiyuan Li
    Optimal Skewed Tiling for Cache Locality Enhancement. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:37- [Conf]
  27. Zhiyuan Li
    Software Assistance for Directory-Based Caches. [Citation Graph (0, 0)][DBLP]
    IPPS, 1994, pp:151-157 [Conf]
  28. Zhiyuan Li, Cheng Wang, Rong Xu
    Task Allocation for Distributed Multimedia Processing on Wirelessly Networked Handheld Devices. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  29. Zhiyuan Li, Walid A. Abu-Sufah
    A Technique for Reducing Synchronization Overhead in Large Scale Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1985, pp:284-291 [Conf]
  30. David J. Kuck, Edward S. Davidson, Duncan H. Lawrie, Ahmed H. Sameh, Chuan-Qi Zhu, Alexander V. Veidenbaum, Jeff Konicek, Pen-Chung Yew, Kyle Gallivan, William Jalby, Harry A. G. Wijshoff, Randall Bramley, U. M. Yang, Perry A. Emrath, David A. Padua, Rudolf Eigenmann, Jay Hoeflinger, Greg Jaxon, Zhiyuan Li, T. Murphy, John T. Andrews, Stephen W. Turner
    The Cedar System and an Initial Performance Study. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:213-223 [Conf]
  31. Rong Xu, Zhiyuan Li
    Using cache mapping to improve memory performance handheld devices. [Citation Graph (0, 0)][DBLP]
    ISPASS, 2004, pp:106-114 [Conf]
  32. Yonghua Ding, Zhiyuan Li
    An Adaptive Scheme for Dynamic Parallelization. [Citation Graph (0, 0)][DBLP]
    LCPC, 2001, pp:274-289 [Conf]
  33. Yonghua Ding, Zhiyuan Li
    Operation Reuse on Handheld Devices (Extended Abstract). [Citation Graph (0, 0)][DBLP]
    LCPC, 2003, pp:273-287 [Conf]
  34. Rudolf Eigenmann, Jay Hoeflinger, Zhiyuan Li, David A. Padua
    Experience in the Automatic Parallelization of Four Perfect-Benchmark Programs. [Citation Graph (0, 0)][DBLP]
    LCPC, 1991, pp:65-83 [Conf]
  35. Zhiyuan Li, Jenn-Yuan Tsai, Xin Wang, Pen-Chung Yew, Bess Zheng
    Compiler Techniques for Concurrent Multithreading with Hardware Speculation Support. [Citation Graph (0, 0)][DBLP]
    LCPC, 1996, pp:175-191 [Conf]
  36. Trung N. Nguyen, Junjie Gu, Zhiyuan Li
    An Interprocedural Parallelizing Compiler and Its Support for Memory Hierarchy Research. [Citation Graph (0, 0)][DBLP]
    LCPC, 1995, pp:96-110 [Conf]
  37. Yonghong Song, Zhiyuan Li
    A Compiler Framework for Tiling Imperfectly-Nested Loops. [Citation Graph (0, 0)][DBLP]
    LCPC, 1999, pp:185-200 [Conf]
  38. Yonghong Song, Cheng Wang, Zhiyuan Li
    Locality Enhancement by Array Contraction. [Citation Graph (0, 0)][DBLP]
    LCPC, 2001, pp:132-146 [Conf]
  39. Rong Xu, Zhiyuan Li
    A sample-based cache mapping scheme. [Citation Graph (0, 0)][DBLP]
    LCTES, 2005, pp:166-174 [Conf]
  40. Yonghong Song, Zhiyuan Li
    New Tiling Techniques to Improve Cache Temporal Locality. [Citation Graph (0, 0)][DBLP]
    PLDI, 1999, pp:215-228 [Conf]
  41. Cheng Wang, Zhiyuan Li
    Parametric analysis for adaptive computation offloading. [Citation Graph (0, 0)][DBLP]
    PLDI, 2004, pp:119-130 [Conf]
  42. Junjie Gu, Zhiyuan Li, Gyungho Lee
    Experience with Efficient Array Data-Flow Analysis for Array Privatization. [Citation Graph (0, 0)][DBLP]
    PPOPP, 1997, pp:157-167 [Conf]
  43. Zhiyuan Li, Pen-Chung Yew
    Efficient Interprocedural Analysis for Program Parallelization and Restructuring. [Citation Graph (0, 0)][DBLP]
    PPOPP/PPEALS, 1988, pp:85-99 [Conf]
  44. Yonghua Ding, Zhiyuan Li
    A Compiler Analysis of Interprocedural Data Communication. [Citation Graph (0, 0)][DBLP]
    SC, 2003, pp:11- [Conf]
  45. Junjie Gu, Zhiyuan Li, Gyungho Lee
    Symbolic Array Dataflow Analysis for Array Privatization and Program Parallelization. [Citation Graph (0, 0)][DBLP]
    SC, 1995, pp:- [Conf]
  46. Douglas Herbert, Yung-Hsiang Lu, Saurabh Bagchi, Zhiyuan Li
    Detection and Repair of Software Errors in Hierarchical Sensor Networks. [Citation Graph (0, 0)][DBLP]
    SUTC (1), 2006, pp:403-410 [Conf]
  47. Zhiyuan Li, Mingyan Yu, Jianguo Ma
    A Rail-to-Rail I/O Operational Amplifier with 0.5% gm Fluctuation Using Double P-channel Differential Input Pairs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:563-568 [Conf]
  48. Zhiyuan Li, Junjie Gu
    A Hierarchical Reasoning System for Automatic Program Parallelization. [Citation Graph (0, 0)][DBLP]
    International Journal on Artificial Intelligence Tools, 2000, v:9, n:3, pp:417-435 [Journal]
  49. Zhiyuan Li, Pen-Chung Yew
    Introduction. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 1998, v:26, n:5, pp:539-540 [Journal]
  50. Zhiyuan Li, Pen-Chung Yew
    Introduction. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 1998, v:26, n:6, pp:639-640 [Journal]
  51. Yonghong Song, Cheng Wang, Zhiyuan Li
    A Polynomial-Time Algorithm for Memory Space Reduction. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2005, v:33, n:1, pp:1-33 [Journal]
  52. Jenn-Yuan Tsai, Zhenzhen Jiang, Zhiyuan Li, David J. Lilja, Xin Wang, Pen-Chung Yew, Bixia Zheng, Stephen J. Schwinn
    Integrating Parallelizing Compilation Technology and Processor Architecture for Cost-Effective Concurrent multithreading. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1998, v:14, n:1, pp:205-222 [Journal]
  53. Cheng Wang, Zhiyuan Li
    A computation offloading scheme on handheld devices. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2004, v:64, n:6, pp:740-746 [Journal]
  54. Trung N. Nguyen, Zhiyuan Li
    Interprocedural Analysis for Loop Scheduling and Data Allocation. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1998, v:24, n:3-4, pp:477-504 [Journal]
  55. Zhiyuan Li, Edward M. Reingold
    Solution of a Divide-and-Conquer Maximin Recurrence. [Citation Graph (0, 0)][DBLP]
    SIAM J. Comput., 1989, v:18, n:6, pp:1188-1200 [Journal]
  56. Zhiyuan Li, Walid A. Abu-Sufah
    On Reducing Data Synchronization in Multiprocessed Loops. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:1, pp:105-109 [Journal]
  57. Guohua Jin, Zhiyuan Li, Fujie Chen
    An Efficient Solution to the Cache Thrashing Problem Caused by True Data Sharing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:5, pp:527-543 [Journal]
  58. Yonghong Song, Rong Xu, Cheng Wang, Zhiyuan Li
    Improving Data Locality by Array Contraction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:9, pp:1073-1084 [Journal]
  59. Scott Hauck, Zhiyuan Li, Eric J. Schwabe
    Configuration compression for the Xilinx XC6200 FPGA. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:8, pp:1107-1113 [Journal]
  60. Guohua Jin, Zhiyuan Li, Fujie Chen
    A theoretical foundation for program transformations to reduce cache thrashing due to true data sharing. [Citation Graph (0, 0)][DBLP]
    Theor. Comput. Sci., 2001, v:255, n:1-2, pp:449-481 [Journal]
  61. Zhiyuan Li, Yonghong Song
    Automatic tiling of iterative stencil loops. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Program. Lang. Syst., 2004, v:26, n:6, pp:975-1028 [Journal]
  62. Zhiyuan Li, Pen-Chung Yew, Chuan-Qi Zhu
    An Efficient Data Dependence Analysis for Parallelizing Compilers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1990, v:1, n:1, pp:26-34 [Journal]
  63. Zhiyu Shen, Zhiyuan Li, Pen-Chung Yew
    An Empirical Study of Fortran Programs for Parallelizing Compilers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1990, v:1, n:3, pp:356-364 [Journal]
  64. Junjie Gu, Zhiyuan Li
    Efficient Interprocedural Array Data-Flow Analysis for Automatic Program Parallelization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 2000, v:26, n:3, pp:244-261 [Journal]
  65. Peifeng Ni, Zhiyuan Li
    Energy cost analysis of IPSec on handheld devices. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:10, pp:585-594 [Journal]
  66. Changjiu Xian, Yung-Hsiang Lu, Zhiyuan Li
    Energy-Aware Scheduling for Real-Time Multiprocessor Systems with Uncertain Task Execution Time. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:664-669 [Conf]
  67. Zhiyuan Li
    Simultaneous Minimization of Capacity and Conflict Misses. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2007, v:22, n:4, pp:497-504 [Journal]
  68. Katherine Compton, Zhiyuan Li, James Cooley, Stephen Knol, Scott Hauck
    Configuration relocation and defragmentation for run-time reconfigurable computing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:209-220 [Journal]
  69. Douglas Herbert, Vinaitheerthan Sundaram, Yung-Hsiang Lu, Saurabh Bagchi, Zhiyuan Li
    Adaptive correctness monitoring for wireless sensor networks using hierarchical distributed run-time invariant checking. [Citation Graph (0, 0)][DBLP]
    TAAS, 2007, v:2, n:3, pp:- [Journal]

  70. Use of embedded scheduling to compile VHDL for effective parallel simulation. [Citation Graph (, )][DBLP]


  71. Adaptive computation offloading for energy conservation on battery-powered systems. [Citation Graph (, )][DBLP]


  72. A compiler-automated array compression scheme for optimizing memory intensive programs. [Citation Graph (, )][DBLP]


  73. Analyzing memory access intensity in parallel programs on multicore. [Citation Graph (, )][DBLP]


  74. Exploiting idle register classes for fast spill destination. [Citation Graph (, )][DBLP]


  75. A programming environment with runtime energy characterization for energy-aware applications. [Citation Graph (, )][DBLP]


  76. ASYNC Loop Constructs for Relaxed Synchronization. [Citation Graph (, )][DBLP]


  77. Improving parallelism and locality with asynchronous algorithms. [Citation Graph (, )][DBLP]


  78. SeNDORComm: An Energy-Efficient Priority-Driven Communication Layer for Reliable Wireless Sensor Networks. [Citation Graph (, )][DBLP]


  79. A Novel Input Stage Based on DTMOS for Low-Voltage Low-Noise Operational Amplifier. [Citation Graph (, )][DBLP]


  80. The Technical Differences between Serial ATA and Ultra ATA Technology. [Citation Graph (, )][DBLP]


  81. Restructuring Fortran programs for Cedar. [Citation Graph (, )][DBLP]


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