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Hsien-Hsin S. Lee:
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Publications of Author
- Lan Gao, Jun Yang, Marek Chrobak, Youtao Zhang, San Nguyen, Hsien-Hsin S. Lee
A low-cost memory remapping scheme for address bus protection. [Citation Graph (0, 0)][DBLP] PACT, 2006, pp:74-83 [Conf]
- Weidong Shi, Hsien-Hsin S. Lee, Mrinmoy Ghosh, Chenghuai Lu
Architectural Support for High Speed Protection of Memory Integrity and Confidentiality in Multiprocessor Systems. [Citation Graph (0, 0)][DBLP] IEEE PACT, 2004, pp:123-134 [Conf]
- Mongkol Ekpanyapong, Pinar Korkmaz, Hsien-Hsin S. Lee
Choice Predictor for Free. [Citation Graph (0, 0)][DBLP] Asia-Pacific Computer Systems Architecture Conference, 2004, pp:399-413 [Conf]
- Mrinmoy Ghosh, Emre Özer, Stuart Biles, Hsien-Hsin S. Lee
Efficient System-on-Chip Energy Management with a Segmented Bloom Filter. [Citation Graph (0, 0)][DBLP] ARCS, 2006, pp:283-297 [Conf]
- Hsien-Hsin S. Lee, Gary S. Tyson
Region-based caching: an energy-delay efficient memory architecture for embedded processors. [Citation Graph (0, 0)][DBLP] CASES, 2000, pp:120-127 [Conf]
- Xiaotong Zhuang, Tao Zhang, Hsien-Hsin S. Lee, Santosh Pande
Hardware assisted control flow obfuscation for embedded processors. [Citation Graph (0, 0)][DBLP] CASES, 2004, pp:292-302 [Conf]
- Dong Hyuk Woo, Mrinmoy Ghosh, Emre Özer, Stuart Biles, Hsien-Hsin S. Lee
Reducing energy of virtual cache synonym lookup using bloom filters. [Citation Graph (0, 0)][DBLP] CASES, 2006, pp:179-189 [Conf]
- Chinnakrishnan Ballapuram, Kiran Puttaswamy, Gabriel H. Loh, Hsien-Hsin S. Lee
Entropy-based low power data TLB design. [Citation Graph (0, 0)][DBLP] CASES, 2006, pp:304-311 [Conf]
- Martin Schulz, Brian S. White, Sally A. McKee, Hsien-Hsin S. Lee, Jürgen Jeitner
Owl: next generation system monitoring. [Citation Graph (0, 0)][DBLP] Conf. Computing Frontiers, 2005, pp:116-124 [Conf]
- Weidong Shi, Hsien-Hsin S. Lee
Accelerating memory decryption and authentication with frequent value prediction. [Citation Graph (0, 0)][DBLP] Conf. Computing Frontiers, 2007, pp:35-46 [Conf]
- Mikhail Smelyanskiy, Scott A. Mahlke, Edward S. Davidson, Hsien-Hsin S. Lee
Predicate-Aware Scheduling: A Technique for Reducing Resource Constraints. [Citation Graph (0, 0)][DBLP] CGO, 2003, pp:169-178 [Conf]
- Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watewai, Hsien-Hsin S. Lee, Sung Kyu Lim
Profile-guided microarchitectural floorplanning for deep submicron processor design. [Citation Graph (0, 0)][DBLP] DAC, 2004, pp:634-639 [Conf]
- Taeweon Suh, Daehyun Kim, Hsien-Hsin S. Lee
Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs. [Citation Graph (0, 0)][DBLP] DAC, 2005, pp:553-558 [Conf]
- Michael B. Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, Gabriel H. Loh
Microarchitectural floorplanning under performance and thermal tradeoff. [Citation Graph (0, 0)][DBLP] DATE, 2006, pp:1288-1293 [Conf]
- Taeweon Suh, Douglas M. Blough, Hsien-Hsin S. Lee
Supporting Cache Coherence in Heterogeneous Multiprocessor Systems. [Citation Graph (0, 0)][DBLP] DATE, 2004, pp:1150-1157 [Conf]
- Weidong Shi, Hsien-Hsin S. Lee, Chenghuai Lu, Tao Zhang
Attacks and risk analysis for hardware supported software copy protection systems. [Citation Graph (0, 0)][DBLP] Digital Rights Management Workshop, 2004, pp:54-62 [Conf]
- Weidong Shi, Chenghuai Lu, Hsien-Hsin S. Lee
Memory-Centric Security Architecture. [Citation Graph (0, 0)][DBLP] HiPEAC, 2005, pp:153-168 [Conf]
- Hsien-Hsin S. Lee, Mikhail Smelyanskiy, Chris J. Newburn, Gary S. Tyson
Stack Value File: Custom Microarchitecture for the Stack. [Citation Graph (0, 0)][DBLP] HPCA, 2001, pp:5-14 [Conf]
- Weidong Shi, Hsien-Hsin S. Lee, Guofei Gu, Laura Falk, Trevor N. Mudge, Mrinmoy Ghosh
An Intrusion-Tolerant and Self-Recoverable Network Service System Using A Security Enhanced Chip Multiprocessor. [Citation Graph (0, 0)][DBLP] ICAC, 2005, pp:263-273 [Conf]
- Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Hsien-Hsin Sean Lee
Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module Level. [Citation Graph (0, 0)][DBLP] ICCAD, 2003, pp:693-700 [Conf]
- Eric L. Boyd, Waqar Azeem, Hsien-Hsin S. Lee, Tien-Pao Shih, Shih-Hao Hung, Edward S. Davidson
A Hierarchical Approach to Modeling and Improving the Performance of Scientific Applications on the KSR1. [Citation Graph (0, 0)][DBLP] ICPP (3), 1994, pp:188-192 [Conf]
- Xiaotong Zhuang, Hsien-Hsin S. Lee
A Hardware-based Cache Pollution Filtering Mechanism for Aggressive Prefetches. [Citation Graph (0, 0)][DBLP] ICPP, 2003, pp:286-293 [Conf]
- Weidong Shi, Hsien-Hsin S. Lee, Laura Falk, Mrinmoy Ghosh
An Integrated Framework for Dependable and Revivable Architectures Using Multicore Processors. [Citation Graph (0, 0)][DBLP] ISCA, 2006, pp:102-113 [Conf]
- Weidong Shi, Hsien-Hsin S. Lee, Mrinmoy Ghosh, Chenghuai Lu, Alexandra Boldyreva
High Efficiency Counter Mode Security Architecture via Prediction and Precomputation. [Citation Graph (0, 0)][DBLP] ISCA, 2005, pp:14-24 [Conf]
- Mongkol Ekpanyapong, Chinnakrishnan Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee
Wire-driven microarchitectural design space exploration. [Citation Graph (0, 0)][DBLP] ISCAS (2), 2005, pp:1867-1870 [Conf]
- Chinnakrishnan S. Ballapuram, Hsien-Hsin S. Lee, Milos Prvulovic
Synonymous address compaction for energy reduction in data TLB. [Citation Graph (0, 0)][DBLP] ISLPED, 2005, pp:357-362 [Conf]
- Hsien-Hsin S. Lee, Chinnakrishnan S. Ballapuram
Energy efficient D-TLB and data cache using semantic-aware multilateral partitioning. [Citation Graph (0, 0)][DBLP] ISLPED, 2003, pp:306-311 [Conf]
- Hsien-Hsin S. Lee, Gary S. Tyson, Matthew K. Farrens
Eager writeback - a technique for improving bandwidth utilization. [Citation Graph (0, 0)][DBLP] MICRO, 2000, pp:11-21 [Conf]
- Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design. [Citation Graph (0, 0)][DBLP] MICRO, 2006, pp:3-14 [Conf]
- Weidong Shi, Hsien-Hsin S. Lee
Authentication Control Point and Its Implications For Secure Processor Design. [Citation Graph (0, 0)][DBLP] MICRO, 2006, pp:103-112 [Conf]
- Hsien-Hsin S. Lee, Gary S. Tyson, Matthew K. Farrens
Improving Bandwidth Utilization using Eager Writeback. [Citation Graph (0, 0)][DBLP] J. Instruction-Level Parallelism, 2001, v:3, n:, pp:- [Journal]
- Chenghuai Lu, Tao Zhang, Weidong Shi, Hsien-Hsin S. Lee
M-TREE: A high efficiency security architecture for protecting integrity and privacy of software. [Citation Graph (0, 0)][DBLP] J. Parallel Distrib. Comput., 2006, v:66, n:9, pp:1116-1128 [Journal]
- Joshua B. Fryman, Chad Huneycutt, Hsien-Hsin S. Lee, Kenneth M. Mackenzie, David E. Schimmel
Energy-Efficient Network Memory for Ubiquitous Devices. [Citation Graph (0, 0)][DBLP] IEEE Micro, 2003, v:23, n:5, pp:60-70 [Journal]
- Taeweon Suh, Hsien-Hsin S. Lee, Douglas M. Blough
Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 1. [Citation Graph (0, 0)][DBLP] IEEE Micro, 2004, v:24, n:4, pp:33-41 [Journal]
- Taeweon Suh, Hsien-Hsin S. Lee, Douglas M. Blough
Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 2. [Citation Graph (0, 0)][DBLP] IEEE Micro, 2004, v:24, n:5, pp:70-78 [Journal]
- Weidong Shi, Hsien-Hsin S. Lee, Chenghuai Lu, Mrinmoy Ghosh
Towards the issues in architectural support for protection of software execution. [Citation Graph (0, 0)][DBLP] SIGARCH Computer Architecture News, 2005, v:33, n:1, pp:6-15 [Journal]
- Xiaotong Zhuang, Hsien-Hsin S. Lee
Reducing Cache Pollution via Dynamic Data Prefetch Filtering. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 2007, v:56, n:1, pp:18-31 [Journal]
- Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watewai, Hsien-Hsin S. Lee, Sung Kyu Lim
Profile-guided microarchitectural floor planning for deep submicron processor design. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1289-1300 [Journal]
- Richard M. Yoo, Han Lee, Kingsum Chow, Hsien-Hsin S. Lee
Constructing a Non-Linear Model with Neural Networks for Workload Characterization. [Citation Graph (0, 0)][DBLP] IISWC, 2006, pp:150-159 [Conf]
Thermal optimization in multi-granularity multi-core floorplanning. [Citation Graph (, )][DBLP]
A unified methodology for power supply noise reduction in modern microarchitecture design. [Citation Graph (, )][DBLP]
Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling. [Citation Graph (, )][DBLP]
Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors. [Citation Graph (, )][DBLP]
COMPASS: a programmable data prefetcher using idle GPU shaders. [Citation Graph (, )][DBLP]
An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems. [Citation Graph (, )][DBLP]
InfoShield: a security architecture for protecting information usage in memory. [Citation Graph (, )][DBLP]
Pre-bond testable low-power clock tree design for 3D stacked ICs. [Citation Graph (, )][DBLP]
Virtual Exclusion: An architectural approach to reducing leakage energy in caches for multiprocessor systems. [Citation Graph (, )][DBLP]
Optimizing Katsevich image reconstruction algorithm on multicore processors. [Citation Graph (, )][DBLP]
Security refresh: prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping. [Citation Graph (, )][DBLP]
Way guard: a segmented counting bloom filter approach to reducing energy for set-associative caches. [Citation Graph (, )][DBLP]
SHARK: Architectural support for autonomic protection against stealth by rootkit exploits. [Citation Graph (, )][DBLP]
Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs. [Citation Graph (, )][DBLP]
Improving TLB energy for java applications on JVM. [Citation Graph (, )][DBLP]
Adaptive transaction scheduling for transactional memory systems. [Citation Graph (, )][DBLP]
Kicking the tires of software transactional memory: why the going gets tough. [Citation Graph (, )][DBLP]
Architectural evaluation of 3D stacked RRAM caches. [Citation Graph (, )][DBLP]
Extending Amdahl's Law for Energy-Efficient Computing in the Many-Core Era. [Citation Graph (, )][DBLP]
Test Challenges for 3D Integrated Circuits. [Citation Graph (, )][DBLP]
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