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Milos Prvulovic: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. María Jesús Garzarán, Milos Prvulovic, Víctor Viñals, José María Llabería, Lawrence Rauchwerger, Josep Torrellas
    Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2003, pp:170-0 [Conf]
  2. María Jesús Garzarán, Milos Prvulovic, Ye Zhang, Josep Torrellas, Alin Jula, Hao Yu, Lawrence Rauchwerger
    Architectural Support for Parallel Reductions in Scalable Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:243-0 [Conf]
  3. Brian Rogers, Milos Prvulovic, Yan Solihin
    Efficient data protection for distributed shared memory multiprocessors. [Citation Graph (0, 0)][DBLP]
    PACT, 2006, pp:84-94 [Conf]
  4. Mazen Kharbutli, Xiaowei Jiang, Yan Solihin, Guru Venkataramani, Milos Prvulovic
    Comprehensively and efficiently protecting the heap. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2006, pp:207-218 [Conf]
  5. Jianli Shen, Guru Venkataramani, Milos Prvulovic
    Tradeoffs in fine-grained heap memory protection. [Citation Graph (0, 0)][DBLP]
    ASID, 2006, pp:52-57 [Conf]
  6. María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas
    Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:191-202 [Conf]
  7. Francis H. Dang, María Jesús Garzarán, Milos Prvulovic, Ye Zhang, Alin Jula, Hao Yu, Nancy M. Amato, Lawrence Rauchwerger, Josep Torrellas
    SmartApps: An Application Centric Approach to High Performance Computing: Compiler-Assisted Software and Hardware Support for Reduction Operations. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  8. Sumit Roy, Raj Kumar, Milos Prvulovic
    Improving System Performance with Compressed Memory. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2001, pp:66- [Conf]
  9. Milos Prvulovic, María Jesús Garzarán, Lawrence Rauchwerger, Josep Torrellas
    Removing architectural bottlenecks to the scalability of speculative parallelization. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:204-215 [Conf]
  10. Milos Prvulovic, Josep Torrellas
    ReEnact: Using Thread-Level Speculation Mechanisms to Debug Data Races in Multithreaded Codes. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:110-121 [Conf]
  11. Milos Prvulovic, Josep Torrellas, Zheng Zhang
    ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:111-122 [Conf]
  12. Chenyu Yan, Daniel Englender, Milos Prvulovic, Brian Rogers, Yan Solihin
    Improving Cost, Performance, and Security of Memory Encryption and Authentication. [Citation Graph (0, 0)][DBLP]
    ISCA, 2006, pp:179-190 [Conf]
  13. Chinnakrishnan S. Ballapuram, Hsien-Hsin S. Lee, Milos Prvulovic
    Synonymous address compaction for energy reduction in data TLB. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:357-362 [Conf]
  14. José F. Martínez, Jose Renau, Michael C. Huang, Milos Prvulovic, Josep Torrellas
    Cherry: checkpointed early resource recycling in out-of-order microprocessors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:3-14 [Conf]
  15. Rithin Shetty, Mazen Kharbutli, Yan Solihin, Milos Prvulovic
    HeapMon: A helper-thread approach to programmable, automatic, and low-overhead memory bug detection. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2006, v:50, n:2-3, pp:261-276 [Journal]
  16. Brian Rogers, Yan Solihin, Milos Prvulovic
    Memory predecryption: hiding the latency overhead of memory encryption. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:1, pp:27-33 [Journal]
  17. María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas
    Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors. [Citation Graph (0, 0)][DBLP]
    TACO, 2005, v:2, n:3, pp:247-279 [Journal]

  18. MemTracker: Efficient and Programmable Support for Memory Access Monitoring and Debugging. [Citation Graph (, )][DBLP]

  19. CORD: cost-effective (and nearly overhead-free) order-recording and data race detection. [Citation Graph (, )][DBLP]

  20. FlexiTaint: A programmable accelerator for dynamic taint propagation. [Citation Graph (, )][DBLP]

  21. Single-level integrity and confidentiality protection for distributed shared memory multiprocessors. [Citation Graph (, )][DBLP]

  22. PEEP: Exploiting predictability of memory dependences in SMT processors. [Citation Graph (, )][DBLP]

  23. Effective memory protection using dynamic tainting. [Citation Graph (, )][DBLP]

  24. Using Address Independent Seed Encryption and Bonsai Merkle Trees to Make Secure Processors OS- and Performance-Friendly. [Citation Graph (, )][DBLP]

  25. The Bulk Multicore architecture for improved programmability. [Citation Graph (, )][DBLP]

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