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Josep Torrellas: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Josep Torrellas, Anoop Gupta, John L. Hennessy
    Characterizing the Caching and Synchronization Performance of a Multiprocessor Operating System. [Citation Graph (1, 0)][DBLP]
    ASPLOS, 1992, pp:162-174 [Conf]
  2. María Jesús Garzarán, Milos Prvulovic, Víctor Viñals, José María Llabería, Lawrence Rauchwerger, Josep Torrellas
    Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2003, pp:170-0 [Conf]
  3. María Jesús Garzarán, Milos Prvulovic, Ye Zhang, Josep Torrellas, Alin Jula, Hao Yu, Lawrence Rauchwerger
    Architectural Support for Parallel Reductions in Scalable Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:243-0 [Conf]
  4. Venkata Krishnan, Josep Torrellas
    An Direct-Execution Framework for Fast and Accurate Simulation of Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1998, pp:286-293 [Conf]
  5. Venkata Krishnan, Josep Torrellas
    The Need for Fast Communication in Hardware-Based Speculative Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1999, pp:24-33 [Conf]
  6. Anthony-Trung Nguyen, Josep Torrellas
    Design Trade-Offs in High-Throughput Coherence Controllers. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2003, pp:194-205 [Conf]
  7. José F. Martínez, Josep Torrellas
    Speculative synchronization: applying thread-level speculation to explicitly parallel applications. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2002, pp:18-29 [Conf]
  8. Paul Sack, Brian E. Bliss, Zhiqiang Ma, Paul Petersen, Josep Torrellas
    Accurate and efficient filtering for the Intel thread checker race detector. [Citation Graph (0, 0)][DBLP]
    ASID, 2006, pp:34-41 [Conf]
  9. Smruti R. Sarangi, Brian Greskamp, Josep Torrellas
    CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging. [Citation Graph (0, 0)][DBLP]
    DSN, 2006, pp:301-312 [Conf]
  10. Radu Teodorescu, Josep Torrellas
    Prototyping Architectural Support for Program Rollback Using FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:23-32 [Conf]
  11. Marcelo H. Cintra, Josep Torrellas
    Speculative Multithreading Eliminating Squashes through Learning Cross-Thread Violations in Speculative Parallelization for Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:43-54 [Conf]
  12. Sujoy Basu, Josep Torrellas
    Enhancing Memory Use in Simple Coma: Multiplexed Simple Coma. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:152-161 [Conf]
  13. María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas
    Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:191-202 [Conf]
  14. Russell M. Clapp, Ashwini K. Nanda, Josep Torrellas
    Second Workshop on Computer Architecture Evaluation Using Commercial Workloads. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:322- [Conf]
  15. Jaejin Lee, Yan Solihin, Josep Torrellas
    Automatically Mapping Code on an Intelligent Memory Architecture. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:121-0 [Conf]
  16. Alain Raynaud, Zheng Zhang, Josep Torrellas
    Distance-Adaptive Update Protocols for Scalable Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:323-334 [Conf]
  17. Josep Torrellas, Chun Xia, Russell L. Daigle
    Optimizing Instruction Cache Performance for Operating System Intensive Workloads. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:360-369 [Conf]
  18. Josep Torrellas, Liuxi Yang, Anthony-Trung Nguyen
    Toward a Cost-Effective DSM Organization That Exploits Processor-Memory Integration. [Citation Graph (0, 0)][DBLP]
    HPCA, 2000, pp:15-25 [Conf]
  19. Pedro Trancoso, Josep-Lluis Larriba-Pey, Zheng Zhang, Josep Torrellas
    The Memory Performance of DSS Commercial Workloads in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:250-260 [Conf]
  20. Chun Xia, Josep Torrellas
    Improving the Data Cache Performance of Multiprocessor Operating Systems. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:85-94 [Conf]
  21. Liuxi Yang, Josep Torrellas
    Speeding up the Memory Hierarchy in Flat COMA Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:4-13 [Conf]
  22. Ye Zhang, Lawrence Rauchwerger, Josep Torrellas
    Hardware for Speculative Run-Time Parallelization in Distributed Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:162-173 [Conf]
  23. Ye Zhang, Lawrence Rauchwerger, Josep Torrellas
    Hardware for Speculative Parallelization of Partially-Parallel Loops in DSM Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:135-0 [Conf]
  24. Zheng Zhang, Josep Torrellas
    Reducing Remote Conflict Misses: NUMA with Remote Cache versus COMA. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:272-0 [Conf]
  25. Qiang Cao, Josep Torrellas, H. V. Jagadish
    Unified Fine-Granularity Buffering of Index and Data: Approach and Implementation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:175-186 [Conf]
  26. Qiang Cao, Josep Torrellas, Pedro Trancoso, Josep-Lluis Larriba-Pey, Bob Knighten, Youjip Won
    Detailed Characterization of a Quad Pentium Pro Server Running TPC-D. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:108-0 [Conf]
  27. Yi Kang, Wei Huang, Seung-Moon Yoo, Diana Keen, Zhenzhou Ge, Vinh Vi Lam, Josep Torrellas, Pratap Pattnaik
    FlexRAM: Toward an Advanced Intelligent Memory System. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:192-201 [Conf]
  28. Anthony-Trung Nguyen, Maged M. Michael, Arun Sharma, Josep Torrellas
    The Augmint multiprocessor simulation toolkit for Intel x86 architectures. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:486-490 [Conf]
  29. Pedro Trancoso, Josep Torrellas
    Cache Optimization for Memory-Resident Decision Support Commercial Workloads. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:546-0 [Conf]
  30. Yi Kang, Josep Torrellas, Thomas S. Huang
    Use IRAM for Rasterization. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 1998, pp:1010-1013 [Conf]
  31. David Koufaty, Josep Torrellas
    Compiler Support for Data Forwarding in Scalable Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICPP, 1999, pp:181-0 [Conf]
  32. Alex Ramírez, Josep-Lluis Larriba-Pey, Carlos Navarro, Xavi Serrano, Mateo Valero, Josep Torrellas
    Optimization of Instruction Fetch for Decision Support Workloads. [Citation Graph (0, 0)][DBLP]
    ICPP, 1999, pp:238-245 [Conf]
  33. Josep Torrellas, John L. Hennessy
    Estimating the Performance Advantages of Relaxing Consistency in a Shared Memory Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1990, pp:26-34 [Conf]
  34. Josep Torrellas, David Koufaty, David A. Padua
    Comparing the Performance of the DASH and CEDAR Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICPP, 1994, pp:304-308 [Conf]
  35. Josep Torrellas, Monica S. Lam, John L. Hennessy
    Share Data Placement Optimizations to Reduce Multiprocessor Cache Miss Rates. [Citation Graph (0, 0)][DBLP]
    ICPP (2), 1990, pp:266-270 [Conf]
  36. Pedro Trancoso, Josep Torrellas
    The Impact of Speeding up Critical Sections with Data Prefetching and Forwarding. [Citation Graph (0, 0)][DBLP]
    ICPP, Vol. 3, 1996, pp:79-86 [Conf]
  37. David Koufaty, Xiangfeng Chen, David K. Poulsen, Josep Torrellas
    Data Forwarding in Scalable Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1995, pp:255-264 [Conf]
  38. David Koufaty, Josep Torrellas
    Comparing Data Forwarding and Prefetching for Communication-induced Misses in Shared-memory MPs. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1998, pp:53-60 [Conf]
  39. Venkata Krishnan, Josep Torrellas
    Hardware and Software Support for Speculative Execution of Sequential Binaries on a Chip-multiprocessor. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1998, pp:85-92 [Conf]
  40. José F. Martínez, Josep Torrellas, José Duato
    Improving the performance of bristled CC-NUMA systems using virtual channels and adaptivity. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:202-209 [Conf]
  41. Alex Ramírez, Josep-Lluis Larriba-Pey, Carlos Navarro, Josep Torrellas, Mateo Valero
    Software trace cache. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:119-126 [Conf]
  42. Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas
    Thread-Level Speculation on a CMP can be energy efficient. [Citation Graph (0, 0)][DBLP]
    ICS, 2005, pp:219-228 [Conf]
  43. Jose Renau, James Tuck, Wei Liu, Luis Ceze, Karin Strauss, Josep Torrellas
    Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilation. [Citation Graph (0, 0)][DBLP]
    ICS, 2005, pp:179-188 [Conf]
  44. Liuxi Yang, Josep Torrellas
    Optimizing Primary Data Caches for Parallel Scientific Applications: The Pool Buffer Approach. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1996, pp:141-148 [Conf]
  45. Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas
    Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips. [Citation Graph (0, 0)][DBLP]
    Intelligent Memory Systems, 2000, pp:152-159 [Conf]
  46. Yan Solihin, Jaejin Lee, Josep Torrellas
    Adaptively Mapping Code in an Intelligent Memory Architecture. [Citation Graph (0, 0)][DBLP]
    Intelligent Memory Systems, 2000, pp:71-84 [Conf]
  47. Francis H. Dang, María Jesús Garzarán, Milos Prvulovic, Ye Zhang, Alin Jula, Hao Yu, Nancy M. Amato, Lawrence Rauchwerger, Josep Torrellas
    SmartApps: An Application Centric Approach to High Performance Computing: Compiler-Assisted Software and Hardware Support for Reduction Operations. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  48. Venkata Krishnan, Josep Torrellas
    A Clustered Approach to Multithreaded Processors. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP, 1998, pp:627-634 [Conf]
  49. Marcelo H. Cintra, José F. Martínez, Josep Torrellas
    Architectural support for scalable speculative parallelization in shared-memory multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:13-24 [Conf]
  50. Luis Ceze, James Tuck, Josep Torrellas, Calin Cascaval
    Bulk Disambiguation of Speculative Threads in Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2006, pp:227-238 [Conf]
  51. Michael C. Huang, Jose Renau, Josep Torrellas
    Positional Adaptation of Processors: Application to Energy Reduction. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:157-168 [Conf]
  52. Milos Prvulovic, María Jesús Garzarán, Lawrence Rauchwerger, Josep Torrellas
    Removing architectural bottlenecks to the scalability of speculative parallelization. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:204-215 [Conf]
  53. Milos Prvulovic, Josep Torrellas
    ReEnact: Using Thread-Level Speculation Mechanisms to Debug Data Races in Multithreaded Codes. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:110-121 [Conf]
  54. Milos Prvulovic, Josep Torrellas, Zheng Zhang
    ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:111-122 [Conf]
  55. Yan Solihin, Josep Torrellas, Jaejin Lee
    Using a User-Level Memory Thread for Correlation Prefetching. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:171-182 [Conf]
  56. Karin Strauss, Xiaowei Shen, Josep Torrellas
    Flexible Snooping: Adaptive Forwarding and Filtering of Snoops in Embedded-Ring Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2006, pp:327-338 [Conf]
  57. Chun Xia, Josep Torrellas
    Instruction Prefetching of Systems Codes with Layout Optimized for Reduced Cache Misses. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:271-282 [Conf]
  58. Zheng Zhang, Josep Torrellas
    Speeding Up Irregular Applications in Shared-Memory Multiprocessors: Memory Binding and Group Prefetching. [Citation Graph (0, 0)][DBLP]
    ISCA, 1995, pp:188-199 [Conf]
  59. Pin Zhou, Feng Qin, Wei Liu, Yuanyuan Zhou, Josep Torrellas
    iWatcher: Efficient Architectural Support for Software Debugging. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:224-237 [Conf]
  60. Michael C. Huang, Jose Renau, Josep Torrellas
    Energy-efficient hybrid wakeup logic. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:196-201 [Conf]
  61. Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas
    L1 data cache decomposition for energy efficiency. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:10-15 [Conf]
  62. Smruti R. Sarangi, Brian Greskamp, Josep Torrellas
    A Model for Timing Errors in Processors with Parameter Variation. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:647-654 [Conf]
  63. Lawrence Rauchwerger, Nancy M. Amato, Josep Torrellas
    SmartApps: An Application Centric Approach to High Performance Computing. [Citation Graph (0, 0)][DBLP]
    LCPC, 2000, pp:82-96 [Conf]
  64. Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas
    A framework for dynamic energy efficiency and temperature management. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:202-213 [Conf]
  65. José F. Martínez, Jose Renau, Michael C. Huang, Milos Prvulovic, Josep Torrellas
    Cherry: checkpointed early resource recycling in out-of-order microprocessors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:3-14 [Conf]
  66. Pin Zhou, Wei Liu, Long Fei, Shan Lu, Feng Qin, Yuanyuan Zhou, Samuel P. Midkiff, Josep Torrellas
    AccMon: Automatically Detecting Memory-Related Bugs via Program Counter-Based Invariants. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:269-280 [Conf]
  67. Shan Lu, Pin Zhou, Wei Liu, Yuanyuan Zhou, Josep Torrellas
    PathExpander: Architectural Support for Increasing the Path Coverage of Dynamic Bug Detection. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:38-52 [Conf]
  68. Smruti R. Sarangi, Abhishek Tiwari, Josep Torrellas
    Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:26-37 [Conf]
  69. James Tuck, Luis Ceze, Josep Torrellas
    Scalable Cache Miss Handling for High Memory-Level Parallelism. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:409-422 [Conf]
  70. Basilio B. Fraguela, Jose Renau, Paul Feautrier, David A. Padua, Josep Torrellas
    Programming the FlexRAM parallel intelligent memory system. [Citation Graph (0, 0)][DBLP]
    PPOPP, 2003, pp:49-60 [Conf]
  71. Wei Liu, James Tuck, Luis Ceze, Wonsun Ahn, Karin Strauss, Jose Renau, Josep Torrellas
    POSH: a TLS compiler that exploits program structure. [Citation Graph (0, 0)][DBLP]
    PPOPP, 2006, pp:158-167 [Conf]
  72. Josep Torrellas
    Upcoming Architectural Advances in DSM Machines and Their Impact on Programmability. [Citation Graph (0, 0)][DBLP]
    PPSC, 1999, pp:- [Conf]
  73. Ding-Kai Chen, Josep Torrellas, Pen-Chung Yew
    An efficient algorithm for the run-time parallelization of DOACROSS loops. [Citation Graph (0, 0)][DBLP]
    SC, 1994, pp:518-527 [Conf]
  74. Josep Torrellas, Zheng Zhang
    The performance of the Cedar multistage switching network. [Citation Graph (0, 0)][DBLP]
    SC, 1994, pp:265-274 [Conf]
  75. Josep Torrellas, John L. Hennessy, Thierry Weil
    Analysis of Critical Architectural and Program Parameters in a Hierarchical Shared Memory Multiprocessor. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 1990, pp:163-172 [Conf]
  76. Josep Torrellas, Andrew Tucker, Anoop Gupta
    Benefits of Cache-Affinity Scheduling in Shared-Memory Multiprocessors: A Summary. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 1993, pp:272-274 [Conf]
  77. Fredrik Dahlgren, Josep Torrellas
    Cache-Only Memory Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1999, v:32, n:6, pp:72-79 [Journal]
  78. Venkata Krishnan, Josep Torrellas
    The Need for Fast Communication in Hardware-Based Speculative Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2001, v:29, n:1, pp:3-33 [Journal]
  79. Alex Ramírez, Josep-Lluis Larriba-Pey, Carlos Navarro, Mateo Valero, Josep Torrellas
    Software Trace Cache for Commercial Applications. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2002, v:30, n:5, pp:373-395 [Journal]
  80. Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas
    The Design of DEETM: a Framework for Dynamic Energy Efficiency and Temperature Management. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2001, v:3, n:, pp:- [Journal]
  81. Josep Torrellas, Andrew Tucker, Anoop Gupta
    Evaluating the Performance of Cache-Affinity Scheduling in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1995, v:24, n:2, pp:139-151 [Journal]
  82. José F. Martínez, Josep Torrellas
    Speculative Synchronization: Programmability and Performance for Parallel Codes. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:6, pp:126-134 [Journal]
  83. Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas
    Energy-Efficient Thread-Level Speculation. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:1, pp:80-91 [Journal]
  84. Radu Teodorescu, Jun Nakano, Josep Torrellas
    SWICH: A Prototype for Efficient Cache-Level Checkpointing and Rollback. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:5, pp:28-40 [Journal]
  85. Josep Torrellas
    Guest Editor's Introduction: Micro's Top Picks from Microarchitecture Conferences. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:1, pp:8-9 [Journal]
  86. Pin Zhou, Feng Qin, Wei Liu, Yuanyuan Zhou, Josep Torrellas
    iWatcher: Simple, General Architectural Support for Software Debugging. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:6, pp:50-56 [Journal]
  87. Luis Ceze, Karin Strauss, James Tuck, Josep Torrellas, Jose Renau
    CAVA: Using checkpoint-assisted value prediction to hide L2 misses. [Citation Graph (0, 0)][DBLP]
    TACO, 2006, v:3, n:2, pp:182-208 [Journal]
  88. María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas
    Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors. [Citation Graph (0, 0)][DBLP]
    TACO, 2005, v:2, n:3, pp:247-279 [Journal]
  89. Yuanyuan Zhou, Pin Zhou, Feng Qin, Wei Liu, Josep Torrellas
    Efficient and flexible architectural support for dynamic monitoring. [Citation Graph (0, 0)][DBLP]
    TACO, 2005, v:2, n:1, pp:3-33 [Journal]
  90. Venkata Krishnan, Josep Torrellas
    A Chip-Multiprocessor Architecture with Speculative Multithreading. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:9, pp:866-880 [Journal]
  91. Yan Solihin, Jaejin Lee, Josep Torrellas
    Automatic Code Mapping on an Intelligent Memory Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:11, pp:1248-1266 [Journal]
  92. Josep Torrellas, Monica S. Lam, John L. Hennessy
    False Sharing ans Spatial Locality in Multiprocessor Caches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:6, pp:651-663 [Journal]
  93. Josep Torrellas, Chun Xia, Russell L. Daigle
    Optimizing the Instruction Cache Performance of the Operating System. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:12, pp:1363-1381 [Journal]
  94. Chun Xia, Josep Torrellas
    Comprehensive Hardware and Software Support for Operating Systems to Exploit. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:5, pp:494-505 [Journal]
  95. Zheng Zhang, Marcelo H. Cintra, Josep Torrellas
    Excel-NUMA: Toward Programmability, Simplicity, and High Performance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:2, pp:256-264 [Journal]
  96. David Koufaty, Xiangfeng Chen, David K. Poulsen, Josep Torrellas
    Data Forwarding in Scalable Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1996, v:7, n:12, pp:1250-1264 [Journal]
  97. Yan Solihin, Jaejin Lee, Josep Torrellas
    Correlation Prefetching with a User-Level Memory Thread. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2003, v:14, n:6, pp:563-580 [Journal]
  98. Josep Torrellas, Zheng Zhang
    The Performance of the Cedar Multistage Switching Network. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1997, v:8, n:4, pp:321-336 [Journal]
  99. Pablo Montesinos, Wei Liu, Josep Torrellas
    Using Register Lifetime Predictions to Protect Register Files against Soft Errors. [Citation Graph (0, 0)][DBLP]
    DSN, 2007, pp:286-296 [Conf]
  100. Abhishek Tiwari, Smruti R. Sarangi, Josep Torrellas
    ReCycle: : pipeline adaptation to tolerate process variation. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:323-334 [Conf]
  101. Luis Ceze, James Tuck, Pablo Montesinos, Josep Torrellas
    BulkSC: bulk enforcement of sequential consistency. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:278-289 [Conf]
  102. Brian Greskamp, Smruti R. Sarangi, Josep Torrellas
    Threshold Voltage Variation Effects on Aging-Related Hard Failure Rates. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1261-1264 [Conf]
  103. Smruti R. Sarangi, Satish Narayanasamy, Bruce Carneal, Abhishek Tiwari, Brad Calder, Josep Torrellas
    Patching Processor Design Errors with Programmable Hardware. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:1, pp:12-25 [Journal]

  104. Paceline: Improving Single-Thread Performance in Nanoscale CMPs through Core Overclocking. [Citation Graph (, )][DBLP]


  105. SoftSig: software-exposed hardware signatures for code analysis and optimization. [Citation Graph (, )][DBLP]


  106. Concurrency control with data coloring. [Citation Graph (, )][DBLP]


  107. Capo: a software-hardware interface for practical deterministic multiprocessor replay. [Citation Graph (, )][DBLP]


  108. Colorama: Architectural Support for Data-Centric Synchronization. [Citation Graph (, )][DBLP]


  109. ReViveI/O: efficient handling of I/O in highly-available rollback-recovery servers. [Citation Graph (, )][DBLP]


  110. Blueshift: Designing processors for timing speculation from the ground up. [Citation Graph (, )][DBLP]


  111. CAP: Criticality analysis for power-efficient speculative multithreading. [Citation Graph (, )][DBLP]


  112. How to build a useful thousand-core manycore system? [Citation Graph (, )][DBLP]


  113. Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors. [Citation Graph (, )][DBLP]


  114. DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Effciently. [Citation Graph (, )][DBLP]


  115. SigRace: signature-based data race detection. [Citation Graph (, )][DBLP]


  116. Uncorq: Unconstrained Snoop Request Delivery in Embedded-Ring Multiprocessors. [Citation Graph (, )][DBLP]


  117. Facelift: Hiding and slowing down aging in multicores. [Citation Graph (, )][DBLP]


  118. The BubbleWrap many-core: popping cores for sequential acceleration. [Citation Graph (, )][DBLP]


  119. Light64: lightweight hardware support for data race detection during systematic testing of parallel programs. [Citation Graph (, )][DBLP]


  120. Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing. [Citation Graph (, )][DBLP]


  121. EVAL: Utilizing processors with variation-induced timing errors. [Citation Graph (, )][DBLP]


  122. BulkCompiler: high-performance sequential consistency through cooperative compiler and hardware support. [Citation Graph (, )][DBLP]


  123. Extreme scale computing: challenges and opportunities. [Citation Graph (, )][DBLP]


  124. Estimating design time for system circuits. [Citation Graph (, )][DBLP]


  125. Two hardware-based approaches for deterministic multiprocessor replay. [Citation Graph (, )][DBLP]


  126. The Bulk Multicore architecture for improved programmability. [Citation Graph (, )][DBLP]


  127. Architectures for Extreme-Scale Computing. [Citation Graph (, )][DBLP]


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The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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