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Dmitry Ponomarev: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose
    SPARTAN: speculative avoidance of register allocations to transient values for performance and energy efficiency. [Citation Graph (0, 0)][DBLP]
    PACT, 2006, pp:265-274 [Conf]
  2. Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose
    Reducing Datapath Energy through the Isolation of Short-Lived Operands. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2003, pp:258-268 [Conf]
  3. Joseph J. Sharkey, Deniz Balkan, Dmitry Ponomarev
    Adaptive reorder buffers for SMT processors. [Citation Graph (0, 0)][DBLP]
    PACT, 2006, pp:244-253 [Conf]
  4. Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose
    AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:124-131 [Conf]
  5. Dmitry Ponomarev, Kanad Ghose, Eugeny Saksonov
    Optimal Polling for Latency-Throughput Tradeoffs in Queue-Based Network Interfaces for Clusters. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2001, pp:86-95 [Conf]
  6. Oguz Ergin, Kanad Ghose, Gurhan Kucuk, Dmitry Ponomarev
    A Circuit-Level Implementation of Fast, Energy-Efficient CMOS Comparators for High-Performance Microprocessors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:118-121 [Conf]
  7. Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad Ghose
    Distributed Reorder Buffer Schemes for Low Power. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:364-370 [Conf]
  8. Dmitry Ponomarev, Vladimir Krylov
    Web Mapping of Real-World Things and its Applications - Product WEBID as a Driving Force for new Supply Chains. [Citation Graph (0, 0)][DBLP]
    ICETE (1), 2004, pp:263-267 [Conf]
  9. Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Aneesh Aggarwal
    Address-Value Decoupling for Early Register Deallocation. [Citation Graph (0, 0)][DBLP]
    ICPP, 2006, pp:337-346 [Conf]
  10. Joseph J. Sharkey, Dmitry Ponomarev
    Balancing ILP and TLP in SMT Architectures through Out-of-Order Instruction Dispatch. [Citation Graph (0, 0)][DBLP]
    ICPP, 2006, pp:329-336 [Conf]
  11. Gurhan Kucuk, Dmitry Ponomarev, Kanad Ghose
    Low-complexity reorder buffer architecture. [Citation Graph (0, 0)][DBLP]
    ICS, 2002, pp:57-66 [Conf]
  12. Gurhan Kucuk, Kanad Ghose, Dmitry Ponomarev, Peter M. Kogge
    Energy: efficient instruction dispatch buffer design for superscalar processors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:237-242 [Conf]
  13. Gurhan Kucuk, Dmitry Ponomarev, Oguz Ergin, Kanad Ghose
    Reducing reorder buffer complexity through selective operand caching. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:235-240 [Conf]
  14. Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose
    Power efficient comparators for long arguments in superscalar processors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:378-383 [Conf]
  15. Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose
    Selective writeback: exploiting transient values for energy-efficiency and performance. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:37-42 [Conf]
  16. Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose
    Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:90-101 [Conf]
  17. Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose, Oguz Ergin
    Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization. [Citation Graph (0, 0)][DBLP]
    PACS, 2004, pp:15-29 [Conf]
  18. Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad Ghose
    Energy Efficient Register Renaming. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:219-228 [Conf]
  19. Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose
    Energy-Efficient Design of the Reorder Buffer. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:289-299 [Conf]
  20. Oguz Ergin, Deniz Balkan, Dmitry Ponomarev, Kanad Ghose
    Early Register Deallocation Mechanisms Using Checkpointed Register Files. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:9, pp:1153-1166 [Journal]
  21. Gurhan Kucuk, Dmitry Ponomarev, Oguz Ergin, Kanad Ghose
    Complexity-Effective Reorder Buffer Designs for Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:6, pp:653-665 [Journal]

  22. Two-Level Reorder Buffers: Accelerating Memory-Bound Applications on SMT Architectures. [Citation Graph (, )][DBLP]


  23. Register Versioning: A Low-Complexity Implementation of Register Renaming in Out-of-Order Microarchitectures. [Citation Graph (, )][DBLP]


  24. Energy-efficient renaming with register versioning. [Citation Graph (, )][DBLP]


  25. A Predictive Model for Cache-Based Side Channels in Multicore and Multithreaded Microprocessors. [Citation Graph (, )][DBLP]


  26. Aggressive Scheduling and Speculation in Multithreaded Architectures: Is it Worth its Salt? [Citation Graph (, )][DBLP]


  27. Metrized Small World Properties Based Data Structure. [Citation Graph (, )][DBLP]


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