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T. N. Vijaykumar: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Brannon Batson, T. N. Vijaykumar
    Reactive-Associative Caches. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:49-60 [Conf]
  2. Chen-Yong Cher, Il Park, T. N. Vijaykumar
    Do Trace Cache, Value Prediction and Prefetching Improve SMT Throughput?. [Citation Graph (0, 0)][DBLP]
    ARCS, 2006, pp:232-251 [Conf]
  3. Mohamed Gomaa, Michael D. Powell, T. N. Vijaykumar
    Heat-and-run: leveraging SMT and CMP to manage power density through the operating system. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2004, pp:260-270 [Conf]
  4. Chen-Yong Cher, Antony L. Hosking, T. N. Vijaykumar
    Software prefetching for mark-sweep garbage collection: hardware analysis and software redesign. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2004, pp:199-210 [Conf]
  5. Ethan Schuchman, T. N. Vijaykumar
    A program transformation and architecture support for quantum uncomputation. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2006, pp:252-263 [Conf]
  6. Amit Agarwal, Kaushik Roy, T. N. Vijaykumar
    Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10778-10783 [Conf]
  7. Sridhar Gopal, T. N. Vijaykumar, James E. Smith, Gurindar S. Sohi
    Speculative Versioning Cache. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:195-205 [Conf]
  8. Jahangir Hasan, Ankit Jalote, T. N. Vijaykumar, Carla E. Brodley
    Heat Stroke: Power-Density-Based Denial of Service in SMT. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:166-177 [Conf]
  9. Hai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykumar, Kaushik Roy
    Deterministic Clock Gating for Microprocessor Power Reduction. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:113-0 [Conf]
  10. Se-Hyun Yang, Michael D. Powell, Babak Falsafi, Kaushik Roy, T. N. Vijaykumar
    An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:147-158 [Conf]
  11. Se-Hyun Yang, Michael D. Powell, Babak Falsafi, T. N. Vijaykumar
    Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:151-0 [Conf]
  12. Chong-liang Ooi, Seon Wook Kim, Il Park, Rudolf Eigenmann, Babak Falsafi, T. N. Vijaykumar
    Multiplex: unifying conventional and speculative thread-level parallelism on a chip multiprocessor. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:368-380 [Conf]
  13. Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar
    Optimizing Replication, Communication, and Capacity Allocation in CMPs. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:357-368 [Conf]
  14. Chris Gniady, Babak Falsafi, T. N. Vijaykumar
    Is SC + ILP=RC? [Citation Graph (0, 0)][DBLP]
    ISCA, 1999, pp:162-171 [Conf]
  15. Mohamed Gomaa, Chad Scarbrough, Irith Pomeranz, T. N. Vijaykumar
    Transient-Fault Recovery for Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:98-109 [Conf]
  16. Mohamed A. Gomaa, T. N. Vijaykumar
    Opportunistic Transient-Fault Detection. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:172-183 [Conf]
  17. Jahangir Hasan, Satish Chandra, T. N. Vijaykumar
    Efficient Use of Memory Bandwidth to Improve Network Processor Throughput. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:300-311 [Conf]
  18. Il Park, Babak Falsafi, T. N. Vijaykumar
    Iimplicitly-Multithreaded Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:39-50 [Conf]
  19. Andreas Moshovos, Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi
    Dynamic Speculation and Synchronization of Data Dependences. [Citation Graph (0, 0)][DBLP]
    ISCA, 1997, pp:181-193 [Conf]
  20. Michael D. Powell, T. N. Vijaykumar
    Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply Voltage. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:72-83 [Conf]
  21. Michael D. Powell, T. N. Vijaykumar
    Exploiting Resonant Behavior to Reduce Inductive Noise. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:288-301 [Conf]
  22. Ethan Schuchman, T. N. Vijaykumar
    Rescue: A Microarchitecture for Testability and Defect Tolerance. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:160-171 [Conf]
  23. Gurindar S. Sohi, Scott E. Breach, T. N. Vijaykumar
    Multiscalar Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1995, pp:414-425 [Conf]
  24. Gurindar S. Sohi, Scott E. Breach, T. N. Vijaykumar
    Multiscalar Processors. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:521-532 [Conf]
  25. T. N. Vijaykumar, Zeshan Chishti
    Wire Delay is Not a Problem for SMT (In the Near Future). [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:40-51 [Conf]
  26. T. N. Vijaykumar, Irith Pomeranz, Karl Cheng
    Transient-Fault Recovery Using Simultaneous Multithreading. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:87-98 [Conf]
  27. Michael D. Powell, T. N. Vijaykumar
    Pipeline muffling and a priori current ramping: architectural techniques to reduce high-frequency inductive noise. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:223-228 [Conf]
  28. Praveen Dongara, T. N. Vijaykumar
    Accelerating private-key cryptography via multithreading on symmetric multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISPASS, 2003, pp:58-69 [Conf]
  29. Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi
    The anatomy of the register file in a multiscalar processor. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:181-190 [Conf]
  30. Chen-Yong Cher, T. N. Vijaykumar
    Skipper: a microarchitecture for exploiting control-flow independence. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:4-15 [Conf]
  31. Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar
    Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:55-66 [Conf]
  32. Hai Li, Chen-Yong Cher, T. N. Vijaykumar, Kaushik Roy
    VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:19-28 [Conf]
  33. Il Park, Chong-liang Ooi, T. N. Vijaykumar
    Reducing Design Complexity of the Load/Store Queue. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:411-422 [Conf]
  34. Il Park, Michael D. Powell, T. N. Vijaykumar
    Reducing register ports for higher speed and lower energy. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:171-182 [Conf]
  35. Michael D. Powell, Amit Agarwal, T. N. Vijaykumar, Babak Falsafi, Kaushik Roy
    Reducing set-associative cache energy via way-prediction and selective direct-mapping. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:54-65 [Conf]
  36. Michael D. Powell, Ethan Schuchman, T. N. Vijaykumar
    Balancing Resource Utilization to Mitigate Power Density in Processor Pipelines. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:294-304 [Conf]
  37. T. N. Vijaykumar, Gurindar S. Sohi
    Task Selection for a Multiscalar Processor. [Citation Graph (0, 0)][DBLP]
    MICRO, 1998, pp:81-92 [Conf]
  38. Troy A. Johnson, Rudolf Eigenmann, T. N. Vijaykumar
    Min-cut program decomposition for thread-level speculation. [Citation Graph (0, 0)][DBLP]
    PLDI, 2004, pp:59-70 [Conf]
  39. Seon Wook Kim, Chong-liang Ooi, Rudolf Eigenmann, Babak Falsafi, T. N. Vijaykumar
    Reference idempotency analysis: a framework for optimizing speculative execution. [Citation Graph (0, 0)][DBLP]
    PPOPP, 2001, pp:2-11 [Conf]
  40. Troy A. Johnson, Rudolf Eigenmann, T. N. Vijaykumar
    Speculative thread decomposition through empirical optimization. [Citation Graph (0, 0)][DBLP]
    PPOPP, 2007, pp:205-214 [Conf]
  41. Jahangir Hasan, T. N. Vijaykumar
    Dynamic pipelining: making IP-lookup truly scalable. [Citation Graph (0, 0)][DBLP]
    SIGCOMM, 2005, pp:205-216 [Conf]
  42. Benjamin A. Kuperman, Carla E. Brodley, Hilmi Ozdoganoglu, T. N. Vijaykumar, Ankit Jalote
    Detection and prevention of stack buffer overflow attacks. [Citation Graph (0, 0)][DBLP]
    Commun. ACM, 2005, v:48, n:11, pp:50-56 [Journal]
  43. T. N. Vijaykumar, Gurindar S. Sohi
    Task Selection for the Multiscalar Architecture. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1999, v:58, n:2, pp:132-158 [Journal]
  44. Alan Fern, Robert Givan, Babak Falsafi, T. N. Vijaykumar
    Dynamic feature selection for hardware prediction. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2006, v:52, n:4, pp:213-234 [Journal]
  45. Mohamed A. Gomaa, Chad Scarbrough, T. N. Vijaykumar, Irith Pomeranz
    Transient-Fault Recovery for Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:6, pp:76-83 [Journal]
  46. Mohamed A. Gomaa, T. N. Vijaykumar
    Opportunistic Transient-Fault Detection. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:1, pp:92-99 [Journal]
  47. Hilmi Ozdoganoglu, T. N. Vijaykumar, Carla E. Brodley, Benjamin A. Kuperman, Ankit Jalote
    SmashGuard: A Hardware Solution to Prevent Security Attacks on the Function Return Address. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:10, pp:1271-1285 [Journal]
  48. Seon Wook Kim, Chong-liang Ooi, Rudolf Eigenmann, Babak Falsafi, T. N. Vijaykumar
    Exploiting reference idempotency to reduce speculative storage overflow. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Program. Lang. Syst., 2006, v:28, n:5, pp:942-965 [Journal]
  49. T. N. Vijaykumar, Sridhar Gopal, James E. Smith, Gurindar S. Sohi
    Speculative Versioning Cache. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2001, v:12, n:12, pp:1305-1317 [Journal]
  50. Hai Li, Swarup Bhunia, Yiran Chen, Kaushik Roy, T. N. Vijaykumar
    DCG: deterministic clock-gating for low-power microprocessor design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:3, pp:245-254 [Journal]
  51. Hai Li, Chen-Yong Cher, Kaushik Roy, T. N. Vijaykumar
    Combined circuit and architectural level variable supply-voltage scaling for low power. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:5, pp:564-576 [Journal]
  52. Ethan Schuchman, T. N. Vijaykumar
    BlackJack: Hard Error Detection with Redundant Threads on SMT. [Citation Graph (0, 0)][DBLP]
    DSN, 2007, pp:327-337 [Conf]
  53. Ahmed M. Amin, Mithuna Thottethodi, T. N. Vijaykumar, Steven Wereley, Stephen C. Jacobson
    Aquacore: a programmable architecture for microfluidics. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:254-265 [Conf]

  54. Joint optimization of idle and cooling power in data centers while maintaining response time. [Citation Graph (, )][DBLP]


  55. Pesticide: Using SMT Processors to Improve Performance of Pointer Bug Detection. [Citation Graph (, )][DBLP]


  56. Timetraveler: exploiting acyclic races for optimizing memory race recording. [Citation Graph (, )][DBLP]


  57. Resource area dilation to reduce power density in throughput servers. [Citation Graph (, )][DBLP]


  58. Shapeshifter: Dynamically changing pipeline width and speed to address process variations. [Citation Graph (, )][DBLP]


  59. Automatic volume management for programmable microfluidics. [Citation Graph (, )][DBLP]


  60. EffiCuts: optimizing packet classification for memory and throughput. [Citation Graph (, )][DBLP]


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