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Publications of Author

1. Michael Behar, Avi Mendelson, Avinoam Kolodny
   Trace Cache Sampling Filter. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2005, pp:255-266 [Conf]
   
2. Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny
   Fast Asynchronous Shift Register for Bit-Serial Communication. [Citation Graph (0, 0)][DBLP]
   ASYNC, 2006, pp:117-127 [Conf]
   
3. Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia Liran, Ran Ginosar, Avinoam Kolodny
   High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link. [Citation Graph (0, 0)][DBLP]
   ASYNC, 2007, pp:3-14 [Conf]
   
4. Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny
   Efficient link capacity and QoS design for network-on-chip. [Citation Graph (0, 0)][DBLP]
   DATE, 2006, pp:9-14 [Conf]
   
5. Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny
   On-chip power distribution grids with multiple supply voltages for high performance integrated circuits. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2005, pp:2-7 [Conf]
   
6. Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny, Radu M. Secareanu
   Maximum effective distance of on-chip decoupling capacitors in power distribution grids. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2006, pp:173-179 [Conf]
   
7. Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny
   Low-leakage repeaters for NoC interconnects. [Citation Graph (0, 0)][DBLP]
   ISCAS (1), 2005, pp:600-603 [Conf]
   
8. Nir Magen, Avinoam Kolodny, Uri Weiser, Nachum Shamir
   Interconnect-power dissipation in a microprocessor. [Citation Graph (0, 0)][DBLP]
   SLIP, 2004, pp:7-13 [Conf]
   
9. Arkadiy Morgenshtein, Michael Moreinis, Israel A. Wagner, Avinoam Kolodny
   Logic Gates as Repeaters (LGR) for Timing Optimization of SoC Interconnects. [Citation Graph (0, 0)][DBLP]
   VLSI-SOC, 2003, pp:99-104 [Conf]
   
10. Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny
    Cost considerations in network on chip. [Citation Graph (0, 0)][DBLP]
    Integration, 2004, v:38, n:1, pp:19-42 [Journal]
    
11. Noam Dolev, Avner Kornfeld, Avinoam Kolodny
    Comparison of Sigma-delta Converter Circuit Architectures in Digital Cmos Technology. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2005, v:14, n:3, pp:515-532 [Journal]
    
12. Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny
    QNoC: QoS architecture and design process for network on chip. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2004, v:50, n:2-3, pp:105-128 [Journal]
    
13. Michael Behar, Avi Mendelson, Avinoam Kolodny
    Trace cache sampling filter. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Comput. Syst., 2007, v:25, n:1, pp:- [Journal]
    
14. Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny
    Routing table minimization for irregular mesh NoCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:942-947 [Conf]
    
15. Michael Sotman, Avinoam Kolodny, Mikhail Popovich, Eby G. Friedman
    On-die decoupling capacitance: frequency domain analysis of activity radius. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
16. Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny
    Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
17. Avinoam Kolodny
    Networks on chips: keeping up with Rent's rule and Moore's law. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:55-56 [Conf]
    
18. Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar, Avinoam Kolodny
    The Power of Priority: NoC Based Distributed Cache Coherency. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:117-126 [Conf]
    
19. Isask'har Walter, Israel Cidon, Ran Ginosar, Avinoam Kolodny
    Access Regulation to Hot-Modules in Wormhole NoCs. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:137-148 [Conf]
    
20. Michael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny
    Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:11, pp:1276-1281 [Journal]
    
21. Y. Elboim, Avinoam Kolodny, Ran Ginosar
    A clock-tuning circuit for system-on-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:4, pp:616-626 [Journal]
    
22. O. Milter, Avinoam Kolodny
    Crosstalk noise reduction in synthesized digital logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1153-1158 [Journal]
    
23. 
    Leveraging application-level requirements in the design of a NoC for a 4G SoC - a case study. [Citation Graph (, )][DBLP]
    
    
24. 
    Power efficient tree-based crosslinks for skew reduction. [Citation Graph (, )][DBLP]
    
    
25. 
    Timing-driven variation-aware nonuniform clock mesh synthesis. [Citation Graph (, )][DBLP]
    
    
26. 
    Performance and Power Aware CMP Thread Allocation Modeling. [Citation Graph (, )][DBLP]
    
    
27. 
    Interconnect power and delay optimization by dynamic programming in gridded design rules. [Citation Graph (, )][DBLP]
    
    
28. 
    Parallel vs. serial on-chip communication. [Citation Graph (, )][DBLP]
    
    
29. 
    Timing optimization in logic with interconnect. [Citation Graph (, )][DBLP]
    
    
30. 
    Utilizing shared data in chip multiprocessors with the nahalal architecture. [Citation Graph (, )][DBLP]
    
    
31. 
    Best of both worlds: A bus enhanced NoC (BENoC). [Citation Graph (, )][DBLP]
    
    
32. 
    The design of a latency constrained, power optimized NoC for a 4G SoC. [Citation Graph (, )][DBLP]
    
    
33. 
    Packet-level static timing analysis for NoCs. [Citation Graph (, )][DBLP]
    
    
34. 
    Nahalal: Cache Organization for Chip Multiprocessors. [Citation Graph (, )][DBLP]