Search the dblp DataBase
Gabriel H. Loh :
[Publications ]
[Author Rank by year ]
[Co-authors ]
[Prefers ]
[Cites ]
[Cited by ]
Publications of Author
Gabriel H. Loh A Simple Divide-and-Conquer Approach for Neural-Class Branch Prediction. [Citation Graph (0, 0)][DBLP ] IEEE PACT, 2005, pp:243-254 [Conf ] Gabriel H. Loh , Dana S. Henry Predicting Conditional Branches With Fusion-Based Hybrid Predictors. [Citation Graph (0, 0)][DBLP ] IEEE PACT, 2002, pp:165-0 [Conf ] Chinnakrishnan Ballapuram , Kiran Puttaswamy , Gabriel H. Loh , Hsien-Hsin S. Lee Entropy-based low power data TLB design. [Citation Graph (0, 0)][DBLP ] CASES, 2006, pp:304-311 [Conf ] Michael B. Healy , Mario Vittes , Mongkol Ekpanyapong , Chinnakrishnan Ballapuram , Sung Kyu Lim , Hsien-Hsin S. Lee , Gabriel H. Loh Microarchitectural floorplanning under performance and thermal tradeoff. [Citation Graph (0, 0)][DBLP ] DATE, 2006, pp:1288-1293 [Conf ] Kiran Puttaswamy , Gabriel H. Loh Thermal analysis of a 3D die-stacked high-performance microprocessor. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2006, pp:19-24 [Conf ] Kiran Puttaswamy , Gabriel H. Loh Dynamic instruction schedulers in a 3-dimensional integration technology. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2006, pp:153-158 [Conf ] Kiran Puttaswamy , Gabriel H. Loh Implementing Caches in a 3D Technology for High Performance Processors. [Citation Graph (0, 0)][DBLP ] ICCD, 2005, pp:525-532 [Conf ] Gabriel H. Loh , Dana S. Henry Applying Machine Learning for Ensemble Branch Predictors. [Citation Graph (0, 0)][DBLP ] IEA/AIE, 2002, pp:264-274 [Conf ] Dana S. Henry , Bradley C. Kuszmaul , Gabriel H. Loh , Rahul Sami Circuits for wide-window superscalar processors. [Citation Graph (0, 0)][DBLP ] ISCA, 2000, pp:236-247 [Conf ] Dana S. Henry , Gabriel H. Loh , Rahul Sami Speculative Clustered Caches for Clustered Processors. [Citation Graph (0, 0)][DBLP ] ISHPC, 2002, pp:281-290 [Conf ] Kiran Puttaswamy , Gabriel H. Loh Implementing Register Files for High-Performance Microprocessors in a Die-Stacked (3D) Technology. [Citation Graph (0, 0)][DBLP ] ISVLSI, 2006, pp:384-392 [Conf ] Peter G. Sassone , D. Scott Wills , Gabriel H. Loh Static strands: safely collapsing dependence chains for increasing embedded power efficiency. [Citation Graph (0, 0)][DBLP ] LCTES, 2005, pp:127-136 [Conf ] Gabriel H. Loh Exploiting data-width locality to increase superscalar execution bandwidth. [Citation Graph (0, 0)][DBLP ] MICRO, 2002, pp:395-405 [Conf ] Bryan Black , Murali Annavaram , Ned Brekelbaum , John DeVale , Lei Jiang , Gabriel H. Loh , Don McCaule , Pat Morrow , Donald W. Nelson , Daniel Pantuso , Paul Reed , Jeff Rupley , Sadasivan Shankar , John Shen , Clair Webb Die Stacking (3D) Microarchitecture. [Citation Graph (0, 0)][DBLP ] MICRO, 2006, pp:469-479 [Conf ] Samantika Subramaniam , Gabriel H. Loh Fire-and-Forget: Load/Store Scheduling with No Store Queue at All. [Citation Graph (0, 0)][DBLP ] MICRO, 2006, pp:273-284 [Conf ] Ranjith Subramanian , Yannis Smaragdakis , Gabriel H. Loh Adaptive Caches: Effective Shaping of Cache Behavior to Workloads. [Citation Graph (0, 0)][DBLP ] MICRO, 2006, pp:385-396 [Conf ] Gabriel H. Loh A time-stamping algorithm for efficient performance estimation of superscalar processors. [Citation Graph (0, 0)][DBLP ] SIGMETRICS/Performance, 2001, pp:72-81 [Conf ] Bradley C. Kuszmaul , Dana S. Henry , Gabriel H. Loh A Comparison of Scalable Superscalar Processors. [Citation Graph (0, 0)][DBLP ] SPAA, 1999, pp:126-137 [Conf ] Yuan Xie , Gabriel H. Loh , Bryan Black , Kerry Bernstein Design space exploration for 3D architectures. [Citation Graph (0, 0)][DBLP ] JETC, 2006, v:2, n:2, pp:65-103 [Journal ] Gabriel H. Loh Width-Partitioned Load Value Predictors. [Citation Graph (0, 0)][DBLP ] J. Instruction-Level Parallelism, 2003, v:5, n:, pp:- [Journal ] Gabriel H. Loh , Dana S. Henry , Arvind Krishnamurthy Exploiting Bias in the Hysteresis Bit of 2-bit Saturating Counters in Branch Predictors. [Citation Graph (0, 0)][DBLP ] J. Instruction-Level Parallelism, 2003, v:5, n:, pp:- [Journal ] Bradley C. Kuszmaul , Dana S. Henry , Gabriel H. Loh A Comparison of Asymptotically Scalable Superscalar Processors. [Citation Graph (0, 0)][DBLP ] Theory Comput. Syst., 2002, v:35, n:2, pp:129-150 [Journal ] Kiran Puttaswamy , Gabriel H. Loh Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors. [Citation Graph (0, 0)][DBLP ] DAC, 2007, pp:622-625 [Conf ] Peter G. Sassone , Jeff Rupley , Edward Brekelbaum , Gabriel H. Loh , Bryan Black Matrix scheduler reloaded. [Citation Graph (0, 0)][DBLP ] ISCA, 2007, pp:335-346 [Conf ] Kiran Puttaswamy , Gabriel H. Loh The impact of 3-dimensional integration on the design of arithmetic units. [Citation Graph (0, 0)][DBLP ] ISCAS, 2006, pp:- [Conf ] Gabriel H. Loh , Yuan Xie , Bryan Black Processor Design in 3D Die-Stacking Technologies. [Citation Graph (0, 0)][DBLP ] IEEE Micro, 2007, v:27, n:3, pp:31-48 [Journal ] Peter G. Sassone , D. Scott Wills , Gabriel H. Loh Static strands: Safely exposing dependence chains for increasing embedded power efficiency. [Citation Graph (0, 0)][DBLP ] ACM Trans. Embedded Comput. Syst., 2007, v:6, n:4, pp:- [Journal ] Thermal optimization in multi-granularity multi-core floorplanning. [Citation Graph (, )][DBLP ] A modular 3d processor for flexible product design and technology migration. [Citation Graph (, )][DBLP ] Scalable Shared-Cache Management by Containing Thrashing Workloads. [Citation Graph (, )][DBLP ] Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors. [Citation Graph (, )][DBLP ] PEEP: Exploiting predictability of memory dependences in SMT processors. [Citation Graph (, )][DBLP ] Store vectors for scalable memory dependence prediction and scheduling. [Citation Graph (, )][DBLP ] Criticality-based optimizations for efficient load processing. [Citation Graph (, )][DBLP ] 3D-Stacked Memory Architectures for Multi-core Processors. [Citation Graph (, )][DBLP ] PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches. [Citation Graph (, )][DBLP ] Use ECP, not ECC, for hard failures in resistive memories. [Citation Graph (, )][DBLP ] Revisiting the performance impact of branch predictor latencies. [Citation Graph (, )][DBLP ] Simulation Differences Between Academia and Industry: A Branch Prediction Case Study. [Citation Graph (, )][DBLP ] Zesto: A cycle-level simulator for highly detailed microarchitecture exploration. [Citation Graph (, )][DBLP ] Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy. [Citation Graph (, )][DBLP ] Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors. [Citation Graph (, )][DBLP ] A Segmented Bloom Filter Algorithm for Efficient Predictors. [Citation Graph (, )][DBLP ] Search in 0.004secs, Finished in 0.007secs