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Shinji Tomita: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. S. Goto, Atsushi Kubota, Toshihiko Tanaka, Masahiro Goshima, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita
    Optimized Code Generation for Heterogeneous Computing Environment using Parallelizing Compiler TINPAR. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1998, pp:426-433 [Conf]
  2. Kazuhiko Ohno, Masahiko Ikawa, Masahiro Goshima, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita
    Efficient Goal Scheduling in Concurrent Logic Language using Type-Based Dependency Analysis. [Citation Graph (0, 0)][DBLP]
    ASIAN, 1997, pp:268-282 [Conf]
  3. Yoshiro Imai, Shinji Tomita
    A Web-Based Education Tool for Collaborative Learning of Assembly Programming. [Citation Graph (0, 0)][DBLP]
    ICWI, 2003, pp:703-710 [Conf]
  4. Yoshiro Imai, Shinji Tomita, Haruo Niimi, Hitoshi Inomo, Wataru Shiraki, Hiroshi Ishikawa
    Development of an Education Tool for Computer System. [Citation Graph (0, 0)][DBLP]
    ICCE, 2002, pp:1309-1310 [Conf]
  5. Hesham Keshk, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita
    Amon: A Parallel Slice Algorithm for Wire Routing. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1995, pp:200-208 [Conf]
  6. Hesham Keshk, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita
    Amon2: A Parallel Wire Routing Algorithm on a Torus Network Parallel Computer. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1996, pp:197-204 [Conf]
  7. Tetsuo Hironaka, Takashi Hashimoto, Keizo Okazaki, Kazuaki Murakami, Shinji Tomita
    Benchmarking a vector-processor prototype based on multithreaded streaming/FIFO vector (MSFV) architecture. [Citation Graph (0, 0)][DBLP]
    ICS, 1992, pp:272-281 [Conf]
  8. Kazuaki Murakami, Shin-ichiro Mori, Akira Fukuda, Toshinori Sueyoshi, Shinji Tomita
    The Kyushu University reconfigurable parallel processor: design of memory and intercommunicaiton architectures. [Citation Graph (0, 0)][DBLP]
    ICS, 1989, pp:351-360 [Conf]
  9. Kazuaki Murakami, Shin-ichiro Mori, Akira Fukuda, Toshinori Sueyoshi, Shinji Tomita
    The Kyushu University Reconfigurable Parallel Processor - Design Philosophy and Architecture. [Citation Graph (0, 0)][DBLP]
    IFIP Congress, 1989, pp:995-1000 [Conf]
  10. Toshiyuki Sakai, Kenji Ohtani, Shinji Tomita
    On-Line, Real-Time, Multiple-Speech Output System. [Citation Graph (0, 0)][DBLP]
    IFIP Congress (1), 1971, pp:686-690 [Conf]
  11. Kiyoshi Shibayama, Shinji Tomita, Hiroshi Hagiwara, Katsuhiro Yamazaki, Toshiaki Kitamura
    Performance Evaluation and Improvement of a Dynamically Microprogrammable Computer with Low-Level Parallelism. [Citation Graph (0, 0)][DBLP]
    IFIP Congress, 1980, pp:181-186 [Conf]
  12. Shinji Tomita
    ISDN and X25 - Response. [Citation Graph (0, 0)][DBLP]
    IFIP Congress, 1986, pp:185-188 [Conf]
  13. Shinji Tomita, Kiyoshi Shibayama, Shigeru Oyanagi, Hiroshi Hagiwara
    Hardware Organization of a Low Level Parallel Processor. [Citation Graph (0, 0)][DBLP]
    IFIP Congress, 1977, pp:855-860 [Conf]
  14. Kazuaki Murakami, Naohiko Irie, Morihiro Kuga, Shinji Tomita
    SIMP (Single Instruction stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 1989, pp:78-85 [Conf]
  15. Shinji Tomita, Kiyoshi Shibayama, Toshiaki Kitamura, Toshiyuki Nakata, Hiroshi Hagiwara
    A User-Microprogrammable, Local Host Computer With Low-Level Parallelism [Citation Graph (0, 0)][DBLP]
    ISCA, 1983, pp:151-157 [Conf]
  16. Shinji Tomita, Kiyoshi Shibayama, Toshiyuki Nakata, Shinji Yuasa, Hiroshi Hagiwara
    A Computer with Low-Level Parallelism QA-2: Its Applications to 3-D Graphics and Prolog/Lisp Machines. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:280-289 [Conf]
  17. Atsushi Kubota, Shogo Tatsumi, Toshihiko Tanaka, Masahiro Goshima, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita
    A Technique to Eliminate Redundant Inter-Processor Communication on Parallelizing Compiler TINPAR. [Citation Graph (0, 0)][DBLP]
    ISHPC, 1997, pp:195-204 [Conf]
  18. Jim Torresen, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita, Olav Landsverk
    Exploiting Parallel Computers to Reduce Neural Network Training Time of Real Applications. [Citation Graph (0, 0)][DBLP]
    ISHPC, 1997, pp:405-414 [Conf]
  19. Shinji Tomita, Akira Namatame
    Bilateral Tradings with and without Strategic Thinking. [Citation Graph (0, 0)][DBLP]
    MABS, 2003, pp:73-88 [Conf]
  20. Masahiro Goshima, Kengo Nishino, Toshiaki Kitamura, Yasuhiko Nakashima, Shinji Tomita, Shin-ichiro Mori
    A high-speed dynamic instruction scheduling scheme for superscalar processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:225-236 [Conf]
  21. Alam Mujahid, Koh Kakusho, Michihiko Minoh, Yasuhiko Nakashima, Shin-ichiro Mori, Shinji Tomita
    Simulating realistic force and shape of virtual cloth with adaptive meshes and its parallel implementation in OpenMP. [Citation Graph (0, 0)][DBLP]
    Parallel and Distributed Computing and Networks, 2004, pp:386-391 [Conf]
  22. Motohiro Takayama, Yuki Shinomoto, Masahiro Goshima, Shin-ichiro Mori, Yasuhiko Nakashima, Shinji Tomita
    Implementation of Cell-Projection Parallel Volume Rendering with Dynamic Load Balancing. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2004, pp:373-382 [Conf]
  23. Shin-ichiro Mori, Hideki Saito, Masahiro Goshima, Mamoru Yanagihara, Takashi Tanaka, David Fraser, Kazuki Joe, Hiroyuki Nitta, Shinji Tomita
    A distributed shared memory multiprocessor ASURA: memory and cache architecture. [Citation Graph (0, 0)][DBLP]
    SC, 1993, pp:740-749 [Conf]
  24. Atsushi Kubota, Shogo Tatsumi, Toshihiko Tanaka, Masahiro Goshima, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita
    A Technique to Eliminate Redundant Inter-Processor Communication on Parallelizing Compiler TINPAR. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 1999, v:27, n:2, pp:97-109 [Journal]
  25. Hiroshi Hagiwara, Shinji Tomita, Shigeru Oyanagi, Kiyoshi Shibayama
    A Dynamically Microprogammable Computer with Low-Level Parallelism. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1980, v:29, n:7, pp:577-595 [Journal]

  26. Low-Complexity Bypass Network Using Small RAM. [Citation Graph (, )][DBLP]


  27. Interactive Fluid Simulation and its Remote Steering Framework with Visual and Haptic Feedback. [Citation Graph (, )][DBLP]


  28. Vertex-preserving Cutting of Elastic Objects. [Citation Graph (, )][DBLP]


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