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Pierre Boulet:
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- Pierre Boulet, Paul Feautrier
Scanning Polyhedra without Do-loops. [Citation Graph (0, 0)][DBLP] IEEE PACT, 1998, pp:4-11 [Conf]
- Vincent Bouchitté, Pierre Boulet, Alain Darte, Yves Robert
Evaluating Array Expressions on Massively Parallel Machines with Communication/ Computation Overlap. [Citation Graph (0, 0)][DBLP] CONPAR, 1994, pp:713-724 [Conf]
- Pierre Boulet, Xavier Redon
Communication Pre-evaluation in HPF. [Citation Graph (0, 0)][DBLP] Euro-Par, 1998, pp:263-272 [Conf]
- Pierre Boulet
Bouclettes: A Fortran Loop Parallelizer. [Citation Graph (0, 0)][DBLP] HPCN Europe, 1996, pp:784-791 [Conf]
- Pierre Boulet, Thomas Brandes
Evaluation of Automatic Parallelization Strategies for HPF Compilers. [Citation Graph (0, 0)][DBLP] HPCN Europe, 1996, pp:778-783 [Conf]
- Ouassila Labbani, Jean-Luc Dekeyser, Pierre Boulet
Mode-Automata Based Methodology for Scade. [Citation Graph (0, 0)][DBLP] HSCC, 2005, pp:386-401 [Conf]
- A. Amar, Pierre Boulet, Jean-Luc Dekeyser, T. Theeuwen
Distributed Process Networks - Using Half FIFO Queues in CORBA. [Citation Graph (0, 0)][DBLP] PARCO, 2003, pp:31-38 [Conf]
- Emmanuel Cagniot, Jean-Luc Dekeyser, Pierre Boulet, Thomas Brandes, Francis Piriou, Georges Marques
Parallelization of a 3D Magnetostatic Code Using High Performance Fortran. [Citation Graph (0, 0)][DBLP] PARELEC, 2000, pp:181-185 [Conf]
- Florent Devin, Pierre Boulet, Jean-Luc Dekeyser, Philippe Marquet
GASPARD - A Visual Parallel Programming Environment. [Citation Graph (0, 0)][DBLP] PARELEC, 2002, pp:145-150 [Conf]
- Ashish Meena, Pierre Boulet
Model Driven Scheduling Framework for Multiprocessor SoC Design. [Citation Graph (0, 0)][DBLP] PPAM, 2005, pp:888-895 [Conf]
- Pierre Boulet, Arnaud Cuccuru, Jean-Luc Dekeyser, Ashish Meena
Model Driven Engineering for Regular MPSoC Co-design. [Citation Graph (0, 0)][DBLP] ReCoSoC, 2005, pp:129-136 [Conf]
- Arnaud Cuccuru, Jean-Luc Dekeyser, Philippe Marquet, Pierre Boulet
Towards UML 2 Extensions for Compact Modeling of Regular Complex Topologies. [Citation Graph (0, 0)][DBLP] MoDELS, 2005, pp:445-459 [Conf]
- Emmanuel Cagniot, Thomas Brandes, Jean-Luc Dekeyser, Francis Piriou, Pierre Boulet, Stéphance Clénet
High Level Parallelization of a 3D Electromagnetic Simulation Code with Irregular Communication Patterns. [Citation Graph (0, 0)][DBLP] VECPAR, 2000, pp:519-528 [Conf]
- Pierre Boulet, Jack Dongarra, Yves Robert, Frédéric Vivien
Static tiling for heterogeneous computing platforms. [Citation Graph (0, 0)][DBLP] Parallel Computing, 1999, v:25, n:5, pp:547-568 [Journal]
- Pierre Boulet, Alain Darte, Georges-André Silber, Frédéric Vivien
Loop Parallelization Algorithms: From Parallelism Extraction to Code Generation. [Citation Graph (0, 0)][DBLP] Parallel Computing, 1998, v:24, n:3-4, pp:421-444 [Journal]
- Pierre Boulet, Jack Dongarra, Fabrice Rastello, Yves Robert, Frédéric Vivien
Algorithmic Issues on Heterogeneous Computing Platforms. [Citation Graph (0, 0)][DBLP] Parallel Processing Letters, 1999, v:9, n:2, pp:197-213 [Journal]
Toward optimized code generation through model-based optimization. [Citation Graph (, )][DBLP]
Architecture Exploration for Efficient Data Transfer and Storage in Data-Parallel Applications. [Citation Graph (, )][DBLP]
Using an MDE Approach for Modeling of Interconnection Networks. [Citation Graph (, )][DBLP]
Projection of the Array-OL Specification Language onto the Kahn Process Network Computation Model. [Citation Graph (, )][DBLP]
Modeling and Formal Validation of High-Performance Embedded Systems. [Citation Graph (, )][DBLP]
Visual Data-Parallel Programming for Signal Processing Applications. [Citation Graph (, )][DBLP]
High Level Loop Transformations for Systematic Signal Processing Embedded Applications. [Citation Graph (, )][DBLP]
UML2 Profile for Modeling Controlled Data Parallel Applications. [Citation Graph (, )][DBLP]
Repetitive Allocation Modelling with MARTE. [Citation Graph (, )][DBLP]
Traceability and Interoperability in Models Transformations. [Citation Graph (, )][DBLP]
Regular Hardware Architecture Modeling with UML2. [Citation Graph (, )][DBLP]
MDA for SoC Design, Intensive Signal Processing Experiment. [Citation Graph (, )][DBLP]
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