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Alain Darte: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Alain Darte
    On the Complexity of Loop Fusion. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1999, pp:149-157 [Conf]
  2. Alain Darte, Steven Derrien, Tanguy Risset
    Hardware/Software Interface for Multi-Dimensional Processor Arrays. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:28-35 [Conf]
  3. Alain Darte, Guillaume Huard
    New Results on Array Contraction. [Citation Graph (0, 0)][DBLP]
    ASAP, 2002, pp:359-370 [Conf]
  4. Alain Darte, Frédéric Vivien
    Revisiting the Decomposition of Karp, Miller and Winograd. [Citation Graph (0, 0)][DBLP]
    ASAP, 1995, pp:13-25 [Conf]
  5. Pierre-Yves Calland, Alain Darte, Yves Robert, Frédéric Vivien
    On the Removal of Anti and Output Dependences. [Citation Graph (0, 0)][DBLP]
    ASAP, 1996, pp:353-364 [Conf]
  6. Alain Darte, Robert Schreiber, Gilles Villard
    Lattice-based memory allocation. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:298-308 [Conf]
  7. Alain Darte
    Two heuristics for task scheduling. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:383-0 [Conf]
  8. Florent Bouchez, Alain Darte, Fabrice Rastello
    On the Complexity of Register Coalescing. [Citation Graph (0, 0)][DBLP]
    CGO, 2007, pp:102-114 [Conf]
  9. Vincent Bouchitté, Pierre Boulet, Alain Darte, Yves Robert
    Evaluating Array Expressions on Massively Parallel Machines with Communication/ Computation Overlap. [Citation Graph (0, 0)][DBLP]
    CONPAR, 1994, pp:713-724 [Conf]
  10. Alain Darte, Yves Robert, Frédéric Vivien
    Loop Parallelization Algorithms. [Citation Graph (0, 0)][DBLP]
    Compiler Optimizations for Scalable Parallel Systems Languages, 2001, pp:141-172 [Conf]
  11. Hadda Cherroun, Alain Darte, Paul Feautrier
    Scheduling under resource constraints using dis-equations. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1067-1072 [Conf]
  12. Alain Darte, Claude G. Diderich, Marc Gengler, Frédéric Vivien
    Scheduling the Computations of a Loop Nest with Respect to a Given Mapping. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2000, pp:405-414 [Conf]
  13. Alain Darte, Georges-André Silber
    Temporary Arrays for Distribution of Loops with Control Dependences. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2000, pp:357-367 [Conf]
  14. Alain Darte, Frédéric Vivien
    On the Optimality of Allen and Kennedy's Algorithm for Parallel Extraction in Nested Loops. [Citation Graph (0, 0)][DBLP]
    Euro-Par, Vol. I, 1996, pp:379-388 [Conf]
  15. Georges-André Silber, Alain Darte
    the NESTOR Library: A Tool for Implementing FORTRAN Source Transformations. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 1999, pp:653-662 [Conf]
  16. Pierre-Yves Calland, Alain Darte, Yves Robert
    A New Guaranteed Heuristic for the Software Pipelining Problem. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1996, pp:261-269 [Conf]
  17. Daniel G. Chavarría-Miranda, Alain Darte, Robert J. Fowler, John M. Mellor-Crummey
    Generalized Multipartitioning for Multi-Dimensional Arrays. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  18. Alain Darte, Robert Schreiber, B. Ramakrishna Rau, Frédéric Vivien
    A Constructive Solution to the Juggling Problem in Processor Array Synthesis. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2000, pp:815-822 [Conf]
  19. Alain Darte, Guillaume Huard
    Loop Shifting for Loop Compaction. [Citation Graph (0, 0)][DBLP]
    LCPC, 1999, pp:415-431 [Conf]
  20. Alain Darte
    Mapping Uniform Loop Nests onto Distributed Memory Architectures. [Citation Graph (0, 0)][DBLP]
    PARCO, 1993, pp:287-294 [Conf]
  21. Alain Darte, Robert Schreiber
    A linear-time algorithm for optimal barrier placement. [Citation Graph (0, 0)][DBLP]
    PPOPP, 2005, pp:26-35 [Conf]
  22. Alain Darte, Guillaume Huard
    Complexity of Multi-dimensional Loop Alignment. [Citation Graph (0, 0)][DBLP]
    STACS, 2002, pp:179-191 [Conf]
  23. Pierre-Yves Calland, Alain Darte, Yves Robert, Frédéric Vivien
    On the Removal of Anti- and Output-Dependences. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 1998, v:26, n:2, pp:285-312 [Journal]
  24. Alain Darte, Guillaume Huard
    Loop Shifting for Loop Compaction. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2000, v:28, n:5, pp:499-534 [Journal]
  25. Alain Darte, John M. Mellor-Crummey, Robert J. Fowler, Daniel G. Chavarría-Miranda
    Generalized multipartitioning of multi-dimensional arrays for parallelizing line-sweep computations. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2003, v:63, n:9, pp:887-911 [Journal]
  26. Alain Darte, Yves Robert
    Affine-by-Statement Scheduling of Uniform and Affine Loop Nests over Parametric. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1995, v:29, n:1, pp:43-59 [Journal]
  27. Pierre Boulet, Alain Darte, Georges-André Silber, Frédéric Vivien
    Loop Parallelization Algorithms: From Parallelism Extraction to Code Generation. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1998, v:24, n:3-4, pp:421-444 [Journal]
  28. Thomas Brandes, Serge Chaumette, Marie Christine Counilh, Jean Roman, Alain Darte, Frederic Desprez, J. C. Mignot
    HPFIT: A Set of Integrated Tools for the Parallelization of Applications Using High Performance Fortran. PART I: HPFIT and the TransTOOL Environment. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1997, v:23, n:1-2, pp:71-87 [Journal]
  29. Pierre-Yves Calland, Alain Darte, Yves Robert, Frédéric Vivien
    Plugging Anti and Output Dependence Removal Techniques Into Loop Parallelization Algorithm. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1997, v:23, n:1-2, pp:251-266 [Journal]
  30. Alain Darte
    On the complexity of loop fusion. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 2000, v:26, n:9, pp:1175-1193 [Journal]
  31. Alain Darte, Yves Robert
    Mapping Uniform Loop Nests Onto Distributed Memory Architectures. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1994, v:20, n:5, pp:679-710 [Journal]
  32. Alain Darte, Leonid Khachiyan, Yves Robert
    Linear Scheduling Is Nearly Optimal. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1991, v:1, n:, pp:73-81 [Journal]
  33. Alain Darte, Yves Robert
    On the Alignment Problem. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1994, v:4, n:, pp:259-270 [Journal]
  34. Alain Darte, Georges-André Silber, Frédéric Vivien
    Combining Retiming and Scheduling Techniques for Loop Parallelization and Loop Tiling. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1997, v:7, n:4, pp:379-392 [Journal]
  35. Alain Darte, Frédéric Vivien
    Revisiting the Decomposition of Karp, Miller and Winograd. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1995, v:5, n:, pp:551-562 [Journal]
  36. Alain Darte, Frédéric Vivien
    Parallelizing Nested Loops with Approximations of Distance Vectors: A Survey. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1997, v:7, n:2, pp:133-144 [Journal]
  37. Alain Darte, Robert Schreiber, Gilles Villard
    Lattice-Based Memory Allocation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:10, pp:1242-1257 [Journal]
  38. Alain Darte, Robert Schreiber, B. Ramakrishna Rau, Frédéric Vivien
    Constructing and exploiting linear schedules with prescribed parallelism. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:1, pp:159-172 [Journal]
  39. Pierre-Yves Calland, Alain Darte, Yves Robert
    Circuit Retiming Applied to Decomposed Software Pipelining. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1998, v:9, n:1, pp:24-35 [Journal]
  40. Alain Darte, Yves Robert
    Constructive Methods for Scheduling Uniform Loop Nests. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1994, v:5, n:8, pp:814-822 [Journal]
  41. Florent Bouchez, Alain Darte, Christophe Guillon, Fabrice Rastello
    Register Allocation: What Does the NP-Completeness Proof of Chaitin et al. Really Prove? Or Revisiting Register Allocation: Why and How. [Citation Graph (0, 0)][DBLP]
    LCPC, 2006, pp:283-298 [Conf]
  42. Christophe Alias, Fabrice Baray, Alain Darte
    Bee+Cl@k: an implementation of lattice-based array contraction in the source-to-source translator rose. [Citation Graph (0, 0)][DBLP]
    LCTES, 2007, pp:73-82 [Conf]
  43. Florent Bouchez, Alain Darte, Fabrice Rastello
    On the complexity of spill everywhere under SSA form. [Citation Graph (0, 0)][DBLP]
    LCTES, 2007, pp:103-112 [Conf]
  44. Florent Bouchez, Alain Darte, Fabrice Rastello
    On the Complexity of Spill Everywhere under SSA Form [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  45. Scheduling Register-Allocated Codes in User-Guided High-Level Synthesis. [Citation Graph (, )][DBLP]


  46. Advanced conservative and optimistic register coalescing. [Citation Graph (, )][DBLP]


  47. Revisiting Out-of-SSA Translation for Correctness, Code Quality and Efficiency. [Citation Graph (, )][DBLP]


  48. Introduction. [Citation Graph (, )][DBLP]


  49. Multi-dimensional Rankings, Program Termination, and Complexity Bounds of Flowchart Programs. [Citation Graph (, )][DBLP]


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