The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

William J. Dally: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. John S. Keen, William J. Dally
    Performance Evaluation of Ephemeral Logging. [Citation Graph (2, 6)][DBLP]
    SIGMOD Conference, 1993, pp:187-196 [Conf]
  2. Abhishek Das, William J. Dally, Peter R. Mattson
    Compiling for stream processing. [Citation Graph (0, 0)][DBLP]
    PACT, 2006, pp:33-42 [Conf]
  3. William J. Dally, Steve Lacy
    VLSI Architecture: Past, Present, and Future. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1999, pp:232-241 [Conf]
  4. Larry R. Dennison, William J. Dally, Thucydides Xanthopoulos
    Low-latency plesiochronous data retiming. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1995, pp:304-315 [Conf]
  5. Nicholas P. Carter, Stephen W. Keckler, William J. Dally
    Hardware Support for Fast Capability-based Addressing. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1994, pp:319-327 [Conf]
  6. William J. Dally
    Micro-Optimization of Floating Point Operations. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1989, pp:283-289 [Conf]
  7. Peter R. Mattson, William J. Dally, Scott Rixner, Ujval J. Kapasi, John D. Owens
    Communication Scheduling. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2000, pp:82-92 [Conf]
  8. John S. Keen, William J. Dally
    XEL: Extended Ephemeral Logging for Log Storage Management. [Citation Graph (0, 0)][DBLP]
    CIKM, 1994, pp:312-321 [Conf]
  9. Prathima Agrawal, William J. Dally, Ahmed K. Ezzat, W. C. Fischer, H. V. Jagadish, A. S. Krishnakumar
    Architecture and Design of the MARS Hardware Accelerator. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:101-107 [Conf]
  10. Prathima Agrawal, R. Tutundjian, William J. Dally
    Algorithms for Accuracy Enhancement in a Hardware Logic Simulator. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:645-648 [Conf]
  11. Andrew Chang, William J. Dally
    Explaining the gap between ASIC and custom power: a custom perspective. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:281-284 [Conf]
  12. William J. Dally, Andrew Chang
    The role of custom design in ASIC Chips. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:643-647 [Conf]
  13. William J. Dally, Brian Towles
    Route Packets, Not Wires: On-Chip Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:684-689 [Conf]
  14. William J. Dally
    Mechanisms for Concurrent Computing. [Citation Graph (0, 0)][DBLP]
    FGCS, 1988, pp:154-156 [Conf]
  15. William J. Dally
    A Universal Parallel Computer Architecture. [Citation Graph (0, 0)][DBLP]
    FGCS, 1992, pp:746-758 [Conf]
  16. Jung Ho Ahn, Mattan Erez, William J. Dally
    Scatter-Add in Data Parallel Architectures. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:132-142 [Conf]
  17. Stuart Fiske, William J. Dally
    Thread Prioritization: A Thread Scheduling Mechanism for Multiple-Context Parallel Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:210-221 [Conf]
  18. Nuwan Jayasena, Mattan Erez, Jung Ho Ahn, William J. Dally
    Stream Register Files with Indexed Access. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:60-72 [Conf]
  19. Peter R. Nuth, William J. Dally
    The Named-State Register File: Implementation and Performance. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:4-13 [Conf]
  20. Brucek Khailany, William J. Dally, Scott Rixner, Ujval J. Kapasi, John D. Owens, Brian Towles
    Exploring the VLSI Scalability of Stream Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:153-164 [Conf]
  21. Li-Shiuan Peh, William J. Dally
    Flit-Reservation Flow Control. [Citation Graph (0, 0)][DBLP]
    HPCA, 2000, pp:73-84 [Conf]
  22. Li-Shiuan Peh, William J. Dally
    A Delay Model and Speculative Architecture for Pipelined Routers. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:255-266 [Conf]
  23. Scott Rixner, William J. Dally, Brucek Khailany, Peter R. Mattson, Ujval J. Kapasi, John D. Owens
    Register Organization for Media Processing. [Citation Graph (0, 0)][DBLP]
    HPCA, 2000, pp:375-386 [Conf]
  24. William J. Dally, Andrew A. Chien, Stuart Fiske, Greg Fyler, Waldemar Horwat, John S. Keen, Richard A. Lethin, Michael D. Noakes, Peter R. Nuth, D. Scott Wills
    The Message Driven Processor: An Integrated Multicomputer Processing Element. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:416-419 [Conf]
  25. Ujval J. Kapasi, William J. Dally, Scott Rixner, John D. Owens, Brucek Khailany
    The Imagine Stream Processor. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:282-288 [Conf]
  26. Brucek Khailany, William J. Dally, Andrew Chang, Ujval J. Kapasi, Jinyung Namkoong, Brian Towles
    VLSI Design and Verification of the Imagine Processor. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:289-294 [Conf]
  27. M.-J. Edward Lee, William J. Dally, Ramin Farjad-Rad, Hiok-Tiaq Ng, Ramesh Senthinathan, John H. Edmondson, John Poulton
    CMOS High-Speed I/Os - Present and Future. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:454-461 [Conf]
  28. Richard A. Lethin, William J. Dally
    MDP Design Tools and Methods. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:424-428 [Conf]
  29. Peter R. Nuth, William J. Dally
    A Mechanism for Efficient Context Switching. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:301-304 [Conf]
  30. Peter R. Nuth, William J. Dally
    The J-Machine Network. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:420-423 [Conf]
  31. John D. Owens, Scott Rixner, Ujval J. Kapasi, Peter R. Mattson, Brian Towles, Ben Serebrin, William J. Dally
    Media Processing Applications on the Imagine Stream Processor. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:295-302 [Conf]
  32. Ben Serebrin, John D. Owens, Chen H. Chen, Stephen P. Crago, Ujval J. Kapasi, Peter R. Mattson, Jinyung Namkoong, Scott Rixner, William J. Dally
    A Stream Processor Development Platform. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:303-0 [Conf]
  33. Ellen Spertus, William J. Dally
    Experiences Implementing Dataflow on a General-Purpose Parallel Computer. [Citation Graph (0, 0)][DBLP]
    ICPP (2), 1991, pp:231-235 [Conf]
  34. James D. Balfour, William J. Dally
    Design tradeoffs for tiled CMP on-chip networks. [Citation Graph (0, 0)][DBLP]
    ICS, 2006, pp:187-198 [Conf]
  35. William J. Dally, Andrew A. Chien, Stuart Fiske, Waldemar Horwat, John S. Keen, Michael Larivee, Richard A. Lethin, Peter R. Nuth, D. Scott Wills
    The J-Machine: A Fine-Gain Concurrent Computer. [Citation Graph (0, 0)][DBLP]
    IFIP Congress, 1989, pp:1147-1153 [Conf]
  36. Brian Towles, William J. Dally
    Guaranteed Scheduling for Switches with Configuration Overhead. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 2002, pp:- [Conf]
  37. Jung Ho Ahn, William J. Dally, Brucek Khailany, Ujval J. Kapasi, Abhishek Das
    Evaluating the Imagine Stream Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:14-25 [Conf]
  38. William J. Dally
    Virtual-Channel Flow Control. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:60-68 [Conf]
  39. William J. Dally, Linda Chao, Andrew A. Chien, Soha Hassoun, Waldemar Horwat, Jon Kaplan, Paul Song, Brian Totty, D. Scott Wills
    Architecture of a Message-Driven Processor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1987, pp:189-196 [Conf]
  40. William J. Dally, Linda Chao, Andrew A. Chien, Soha Hassoun, Waldemar Horwat, Jon Kaplan, Paul Song, Brian Totty, D. Scott Wills
    Architecture of a Message-Driven Processor. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:337-344 [Conf]
  41. William J. Dally, Andrew A. Chien, Stuart Fiske, Waldemar Horwat, Richard A. Lethin, Michael D. Noakes, Peter R. Nuth, Ellen Spertus, Deborah A. Wallach, D. Scott Wills, Andrew Chang, John S. Keen
    Retrospective: the J-machine. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:54-58 [Conf]
  42. William J. Dally, James T. Kajiya
    An Object Oriented Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 1985, pp:154-161 [Conf]
  43. Stuart Fiske, William J. Dally
    The Reconfigurable Arithmetic Processor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:30-36 [Conf]
  44. Stephen W. Keckler, William J. Dally
    Processor Coupling: Integrating Compile Time and Runtime Scheduling for Parallelism. [Citation Graph (0, 0)][DBLP]
    ISCA, 1992, pp:202-213 [Conf]
  45. Stephen W. Keckler, William J. Dally, Daniel Maskit, Nicholas P. Carter, Andrew Chang, Whay Sing Lee
    Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:306-317 [Conf]
  46. John Kim, William J. Dally, Brian Towles, Amit K. Gupta
    Microarchitecture of a High-Radix Router. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:420-431 [Conf]
  47. Ken Mai, Tim Paaske, Nuwan Jayasena, Ron Ho, William J. Dally, Mark Horowitz
    Smart Memories: a modular reconfigurable architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:161-171 [Conf]
  48. Michael D. Noakes, Deborah A. Wallach, William J. Dally
    The J-Machine Multicomputer: An Architectural Evaluation. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:224-235 [Conf]
  49. Scott Rixner, William J. Dally, Ujval J. Kapasi, Peter R. Mattson, John D. Owens
    Memory access scheduling. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:128-138 [Conf]
  50. Steve Scott, Dennis Abts, John Kim, William J. Dally
    The BlackWidow High-Radix Clos Network. [Citation Graph (0, 0)][DBLP]
    ISCA, 2006, pp:16-28 [Conf]
  51. Arjun Singh, William J. Dally, Amit K. Gupta, Brian Towles
    GOAL: A Load-Balanced Adaptive Routing Algorithm for Torus Networks. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:194-205 [Conf]
  52. Ellen Spertus, Seth Copen Goldstein, Klaus E. Schauser, Thorsten von Eicken, David E. Culler, William J. Dally
    Evaluation of Mechanisms for Fine-Grained Parallel Programs in the J-Machine and the CM-5. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:302-313 [Conf]
  53. P. Chiang, William J. Dally, E. Lee
    Monolithic chaotic communications system. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:325-328 [Conf]
  54. Nicholas P. Carter, William J. Dally, Whay Sing Lee, Stephen W. Keckler, Andrew Chang
    Processor Mechanisms for Software Shared Memory. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2000, pp:120-133 [Conf]
  55. Marco Fillo, Stephen W. Keckler, William J. Dally, Nicholas P. Carter, Andrew Chang, Yevgeny Gurevich, Whay Sing Lee
    The M-Machine multicomputer. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:146-156 [Conf]
  56. Ujval J. Kapasi, William J. Dally, Scott Rixner, Peter R. Mattson, John D. Owens, Brucek Khailany
    Efficient conditional operations for data-parallel architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:159-170 [Conf]
  57. Scott Rixner, William J. Dally, Ujval J. Kapasi, Brucek Khailany, Abelardo López-Lagunas, Peter R. Mattson, John D. Owens
    A Bandwidth-efficient Architecture for Media Processing. [Citation Graph (0, 0)][DBLP]
    MICRO, 1998, pp:3-13 [Conf]
  58. William J. Dally, D. Scott Wills
    Universal Mechanisms for Concurrency. [Citation Graph (0, 0)][DBLP]
    PARLE (1), 1989, pp:19-33 [Conf]
  59. William J. Dally, Larry R. Dennison, David Harris, Kinhong Kan, Thucydides Xanthopoulos
    The Reliable Router: A Reliable and High-Performance Communication Substrate for Parallel Computers. [Citation Graph (0, 0)][DBLP]
    PCRCW, 1994, pp:241-255 [Conf]
  60. Waldemar Horwat, Andrew A. Chien, William J. Dally
    Experience with CST: Programming and Implementation. [Citation Graph (0, 0)][DBLP]
    PLDI, 1989, pp:101-109 [Conf]
  61. Andrew A. Chien, William J. Dally
    Concurrent Aggregates (CA). [Citation Graph (0, 0)][DBLP]
    PPOPP, 1990, pp:187-196 [Conf]
  62. Ellen Spertus, William J. Dally
    Evaluating the Locality Benefits of Active Messages. [Citation Graph (0, 0)][DBLP]
    PPOPP, 1995, pp:189-198 [Conf]
  63. Timothy J. Knight, Ji Young Park, Manman Ren, Mike Houston, Mattan Erez, Kayvon Fatahalian, Alex Aiken, William J. Dally, Pat Hanrahan
    Compilation for explicitly managed memory hierarchies. [Citation Graph (0, 0)][DBLP]
    PPOPP, 2007, pp:226-236 [Conf]
  64. J. P. Grossman, William J. Dally
    Point Sample Rendering. [Citation Graph (0, 0)][DBLP]
    Rendering Techniques, 1998, pp:181-192 [Conf]
  65. William J. Dally, Francois Labonte, Abhishek Das, Pat Hanrahan, Jung Ho Ahn, Jayanth Gummaraju, Mattan Erez, Nuwan Jayasena, Ian Buck, Timothy J. Knight, Ujval J. Kapasi
    Merrimac: Supercomputing with Streams. [Citation Graph (0, 0)][DBLP]
    SC, 2003, pp:35- [Conf]
  66. Mattan Erez, Jung Ho Ahn, Ankit Garg, William J. Dally, Eric Darve
    Analysis and Performance Results of a Molecular Modeling Application on Merrimac. [Citation Graph (0, 0)][DBLP]
    SC, 2004, pp:42- [Conf]
  67. Mattan Erez, Nuwan Jayasena, Timothy J. Knight, William J. Dally
    Fault Tolerance Techniques for the Merrimac Streaming Supercomputer. [Citation Graph (0, 0)][DBLP]
    SC, 2005, pp:29- [Conf]
  68. Jung Ho Ahn, Mattan Erez, William J. Dally
    Architecture - The design space of data-parallel memory systems. [Citation Graph (0, 0)][DBLP]
    SC, 2006, pp:80- [Conf]
  69. Kayvon Fatahalian, Daniel Reiter Horn, Timothy J. Knight, Larkhoon Leem, Mike Houston, Ji Young Park, Mattan Erez, Manman Ren, Alex Aiken, William J. Dally, Pat Hanrahan
    Memory - Sequoia: programming the memory hierarchy. [Citation Graph (0, 0)][DBLP]
    SC, 2006, pp:83- [Conf]
  70. John Kim, William J. Dally, Dennis Abts
    Interconnect routing and scheduling - Adaptive routing in high-radix clos network. [Citation Graph (0, 0)][DBLP]
    SC, 2006, pp:92- [Conf]
  71. Thomas L. Sterling, Peter M. Kogge, William J. Dally, Steve Scott, William Gropp, David E. Keyes, Pete Beckman
    Multi-core issues - Multi-Core for HPC: breakthrough or breakdown? [Citation Graph (0, 0)][DBLP]
    SC, 2006, pp:73- [Conf]
  72. Arjun Singh, William J. Dally, Amit K. Gupta, Brian Towles
    Adaptive channel queue routing on k-ary n-cubes. [Citation Graph (0, 0)][DBLP]
    SPAA, 2004, pp:11-19 [Conf]
  73. Arjun Singh, William J. Dally, Brian Towles, Amit K. Gupta
    Locality-preserving randomized oblivious routing on torus networks. [Citation Graph (0, 0)][DBLP]
    SPAA, 2002, pp:9-13 [Conf]
  74. Brian Towles, William J. Dally
    Worst-case traffic for oblivious routing functions. [Citation Graph (0, 0)][DBLP]
    SPAA, 2002, pp:1-8 [Conf]
  75. Brian Towles, William J. Dally, Stephen P. Boyd
    Throughput-centric routing algorithm design. [Citation Graph (0, 0)][DBLP]
    SPAA, 2003, pp:200-209 [Conf]
  76. K. A. Shaw, William J. Dally
    Migration in Single Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    Computer Architecture Letters, 2002, v:1, n:, pp:- [Journal]
  77. Arjun Singh, William J. Dally, Brian Towles, Amit K. Gupta
    Globally Adaptive Load-Balanced Routing on Tori. [Citation Graph (0, 0)][DBLP]
    Computer Architecture Letters, 2004, v:3, n:, pp:- [Journal]
  78. Brian Towles, William J. Dally
    Worst-case Traffic for Oblivious Routing Functions. [Citation Graph (0, 0)][DBLP]
    Computer Architecture Letters, 2002, v:1, n:, pp:- [Journal]
  79. Whay Sing Lee, William J. Dally, Stephen W. Keckler, Nicholas P. Carter, Andrew Chang
    An Efficient, Protected Message Interface. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1998, v:31, n:11, pp:69-75 [Journal]
  80. Ujval J. Kapasi, Scott Rixner, William J. Dally, Brucek Khailany, Jung Ho Ahn, Peter R. Mattson, John D. Owens
    Programmable Stream Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2003, v:36, n:8, pp:54-62 [Journal]
  81. William J. Dally, Charles L. Seitz
    The Torus Routing Chip. [Citation Graph (0, 0)][DBLP]
    Distributed Computing, 1986, v:1, n:4, pp:187-196 [Journal]
  82. William J. Dally, Keith Diefendorff
    Hot Chips 16: Power, Parallelism, and Memory Performance. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:2, pp:8-9 [Journal]
  83. William J. Dally, Marc Tremblay, Allen J. Baum
    Guest Editors' Introduction: Hot Chips 12. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2001, v:21, n:2, pp:13-15 [Journal]
  84. Brucek Khailany, William J. Dally, Ujval J. Kapasi, Peter R. Mattson, Jinyung Namkoong, John D. Owens, Brian Towles, Andrew Chang, Scott Rixner
    Imagine: Media Processing with Streams. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2001, v:21, n:2, pp:35-46 [Journal]
  85. Li-Shiuan Peh, William J. Dally
    A Delay Model for Router Microarchitectures. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2001, v:21, n:1, pp:26-34 [Journal]
  86. William J. Dally
    A Universal Parallel Computer Architecture. [Citation Graph (0, 0)][DBLP]
    New Generation Comput., 1993, v:11, n:3, pp:227-249 [Journal]
  87. William J. Dally, Ujval J. Kapasi, Brucek Khailany, Jung Ho Ahn, Abhishek Das
    Stream Processors: Progammability and Efficiency. [Citation Graph (0, 0)][DBLP]
    ACM Queue, 2004, v:2, n:1, pp:52-62 [Journal]
  88. William J. Dally, Andrew A. Chien
    Object-oriented concurrent programming in CST. [Citation Graph (0, 0)][DBLP]
    SIGPLAN Notices, 1989, v:24, n:4, pp:28-31 [Journal]
  89. William J. Dally
    Performance Analysis of k-Ary n-Cube Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:6, pp:775-785 [Journal]
  90. William J. Dally
    Express Cubes: Improving the Performance of k-Ary n-Cube Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:9, pp:1016-1023 [Journal]
  91. William J. Dally
    A Fast Translation Method for Paging on top of Segmentation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:2, pp:247-250 [Journal]
  92. William J. Dally, Charles L. Seitz
    Deadlock-Free Message Routing in Multiprocessor Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:5, pp:547-553 [Journal]
  93. Stephen W. Keckler, Andrew Chang, Whay Sing Lee, Sandeep Chatterjee, William J. Dally
    Concurrent Event Handling through Multithreading. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:9, pp:903-916 [Journal]
  94. Prathima Agrawal, William J. Dally
    A hardware logic simulation system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:1, pp:19-29 [Journal]
  95. William J. Dally, Randal E. Bryant
    A Hardware Architecture for Switch-Level Simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:239-250 [Journal]
  96. John S. Keen, William J. Dally
    Extended Ehemeral Logging: Log Storage Management for Applications with Long Lived Transactions. [Citation Graph (0, 18)][DBLP]
    ACM Trans. Database Syst., 1997, v:22, n:1, pp:1-42 [Journal]
  97. Brian Towles, William J. Dally
    Guaranteed scheduling for switches with configuration overhead. [Citation Graph (0, 0)][DBLP]
    IEEE/ACM Trans. Netw., 2003, v:11, n:5, pp:835-847 [Journal]
  98. William J. Dally
    Virtual-Channel Flow Control. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1992, v:3, n:2, pp:194-205 [Journal]
  99. William J. Dally, Hiromichi Aoki
    Deadlock-Free Adaptive Routing in Multicomputer Networks Using Virtual Channels. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1993, v:4, n:4, pp:466-475 [Journal]
  100. JongSoo Park, Sung-Boem Park, James D. Balfour, David Black-Schaffer, Christos Kozyrakis, William J. Dally
    Register pointer architecture for efficient embedded processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:600-605 [Conf]
  101. Jung Ho Ahn, Mattan Erez, William J. Dally
    Tradeoff between data-, instruction-, and thread-level parallelism in stream processors. [Citation Graph (0, 0)][DBLP]
    ICS, 2007, pp:126-137 [Conf]
  102. Mattan Erez, Jung Ho Ahn, Jayanth Gummaraju, Mendel Rosenblum, William J. Dally
    Executing irregular scientific applications on stream architectures. [Citation Graph (0, 0)][DBLP]
    ICS, 2007, pp:93-104 [Conf]
  103. John Kim, William J. Dally, Dennis Abts
    Flattened butterfly: a cost-efficient topology for high-radix networks. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:126-137 [Conf]
  104. William J. Dally
    Enabling Technology for On-Chip Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:3- [Conf]
  105. John D. Owens, William J. Dally, Ron Ho, D. N. Jayasimha, Stephen W. Keckler, Li-Shiuan Peh
    Research Challenges for On-Chip Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:5, pp:96-108 [Journal]

  106. Architectural Support for the Stream Execution Model on General-Purpose Processors. [Citation Graph (, )][DBLP]


  107. Stream Scheduling: A Framework to Manage Bulk Operations in a Memory Hierarchy. [Citation Graph (, )][DBLP]


  108. A tuning framework for software-managed memory hierarchies. [Citation Graph (, )][DBLP]


  109. Stream Scheduling: A Framework to Manage Bulk Operations in Memory Hierarchies. [Citation Graph (, )][DBLP]


  110. Scalable Opto-Electronic Network (SOENet). [Citation Graph (, )][DBLP]


  111. Interconnect-Centric Computing. [Citation Graph (, )][DBLP]


  112. Elastic-buffer flow control for on-chip networks. [Citation Graph (, )][DBLP]


  113. Computer Architecture in the Many-Core Era. [Citation Graph (, )][DBLP]


  114. Technology-Driven, Highly-Scalable Dragonfly Topology. [Citation Graph (, )][DBLP]


  115. Indirect adaptive routing on large scale interconnection networks. [Citation Graph (, )][DBLP]


  116. Moving the needle, computer architecture research in academe and industry. [Citation Graph (, )][DBLP]


  117. Future of on-chip interconnection architectures. [Citation Graph (, )][DBLP]


  118. Flattened Butterfly Topology for On-Chip Networks. [Citation Graph (, )][DBLP]


  119. A portable runtime interface for multi-level memory hierarchies. [Citation Graph (, )][DBLP]


  120. Allocator implementations for network-on-chip routers. [Citation Graph (, )][DBLP]


  121. Router designs for elastic buffer on-chip networks. [Citation Graph (, )][DBLP]


  122. Buffer-space efficient and deadlock-free scheduling of stream applications on multi-core architectures. [Citation Graph (, )][DBLP]


  123. Evaluating Bufferless Flow Control for On-chip Networks. [Citation Graph (, )][DBLP]


  124. Topology optimization of interconnection networks. [Citation Graph (, )][DBLP]


  125. Flattened Butterfly Topology for On-Chip Networks. [Citation Graph (, )][DBLP]


  126. Data parallel address architecture. [Citation Graph (, )][DBLP]


  127. Efficient Embedded Computing. [Citation Graph (, )][DBLP]


Search in 0.008secs, Finished in 0.012secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002