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Ravi Nair: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Harold W. Cain, Mikko H. Lipasti, Ravi Nair
    Constraint Graph Analysis of Multithreaded Programs. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2003, pp:4-14 [Conf]
  2. Pradeep K. Dubey, Ravi Nair
    Profile-Driven Generation of Trace Samples. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:217-224 [Conf]
  3. Ravi Nair, Martin E. Hopkins
    Exploiting Instruction Level Parallelism in Processors by Caching Scheduled Groups. [Citation Graph (0, 0)][DBLP]
    ISCA, 1997, pp:13-25 [Conf]
  4. Ravi Nair
    Dynamic path-based branch correlation. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:15-23 [Conf]
  5. Lawrence Rauchwerger, Pradeep K. Dubey, Ravi Nair
    Measuring limits of parallelism and characterizing its vulnerability to resource constraints. [Citation Graph (0, 0)][DBLP]
    MICRO, 1993, pp:105-117 [Conf]
  6. James E. Smith, Ravi Nair
    The Architecture of Virtual Machines. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2005, v:38, n:5, pp:32-38 [Journal]
  7. Ravi Nair
    Effect of increasing chip density on the evolution of computer architectures. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2002, v:46, n:2-3, pp:223-234 [Journal]
  8. Ravi Nair
    Profiling IBM RS/6000 Applications. [Citation Graph (0, 0)][DBLP]
    Int. Journal in Computer Simulation, 1996, v:6, n:1, pp:101-0 [Journal]
  9. Harold W. Cain, Mikko H. Lipasti, Ravi Nair
    Constraint Graph Analysis of Multithreaded Programs. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2004, v:6, n:, pp:- [Journal]
  10. Ravi Nair
    Optimal 2-Bit Branch Predictors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:5, pp:698-702 [Journal]
  11. Ravi Nair
    A Simple Yet Effective Technique for Global Wiring. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:2, pp:165-172 [Journal]
  12. Ravi Nair, C. Leonard Berman, Peter S. Hauge, Ellen J. Yoffa
    Generation of performance constraints for layout. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:8, pp:860-874 [Journal]
  13. C. Andrew Neff, Ravi Nair
    A Ranking Algorithm for MOS Circuit Layouts. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:1, pp:17-21 [Journal]

  14. Models for energy-efficient approximate computing. [Citation Graph (, )][DBLP]


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