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## Search the dblp DataBase
Jeffrey J. Joyce:
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## Publications of Author- Jeffrey J. Joyce
**Integration of CASE into undergraduate education.**[Citation Graph (0, 0)][DBLP] CASCON, 1993, pp:128-137 [Conf] - Carl-Johan H. Seger, Jeffrey J. Joyce
**A Two-Level Formal Verification Methodology using HOL and COSMOS.**[Citation Graph (0, 0)][DBLP] CAV, 1991, pp:299-309 [Conf] - Jeffrey J. Joyce, Carl-Johan H. Seger
**Linking BDD-Based Symbolic Evaluation to Interactive Theorem-Proving.**[Citation Graph (0, 0)][DBLP] DAC, 1993, pp:469-474 [Conf] - Jeffrey J. Joyce
**Formal Specification and Verification of Asynchronous Processes in Higher-Order Logic.**[Citation Graph (0, 0)][DBLP] Specification and Verification of Concurrent Systems, 1988, pp:384-409 [Conf] - J. H. Andrews, Nancy A. Day, Jeffrey J. Joyce
**Using a Formal Description Technique to Model Aspects of a Global Air Traffic Telecommunications Network.**[Citation Graph (0, 0)][DBLP] FORTE, 1997, pp:417-432 [Conf] - Nancy A. Day, Jeffrey J. Joyce
**A Framework for Multi-Notation Requirements Specification and Analysis.**[Citation Graph (0, 0)][DBLP] ICRE, 2000, pp:39-48 [Conf] - Jeffrey J. Joyce
**Totally Verified Systems: Linking Verified Software to Verified Hardware.**[Citation Graph (0, 0)][DBLP] Hardware Specification, Verification and Synthesis, 1989, pp:177-201 [Conf] - Nancy A. Day, Jeffrey J. Joyce
**The Semantics of Statecharts in HOL.**[Citation Graph (0, 0)][DBLP] HUG, 1993, pp:338-351 [Conf] - Nancy A. Day, Jeffrey J. Joyce
**Symbolic Functional Evaluation.**[Citation Graph (0, 0)][DBLP] TPHOLs, 1999, pp:341-358 [Conf] - Jeffrey J. Joyce, Nancy A. Day, Michael R. Donat
**S: A Machine Readable Specification Notation based on Higher Order Logic.**[Citation Graph (0, 0)][DBLP] TPHOLs, 1994, pp:285-299 [Conf] - Jeffrey J. Joyce, Carl-Johan H. Seger
**The HOL-Voss System: Model-Checking inside a General-Purpose Theorem-Prover.**[Citation Graph (0, 0)][DBLP] HUG, 1993, pp:185-198 [Conf] - Sreeranga P. Rajan, Jeffrey J. Joyce, Carl-Johan H. Seger
**From Abstract Data Types to Shift Registers: A Case Study in Formal Specification and Verification at Differing Levels of Abstraction using Theorem Proving and Symbolic Simulation.**[Citation Graph (0, 0)][DBLP] HUG, 1993, pp:489-500 [Conf] - Zheng Zhu, Jeffrey J. Joyce, Carl-Johan H. Seger
**Verification of the Tamarack-3 Microprocessor in a Hybrid Verification Environment.**[Citation Graph (0, 0)][DBLP] HUG, 1993, pp:253-266 [Conf]
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