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Hans Vandierendonck:
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Publications of Author
- Lieven Eeckhout, Hans Vandierendonck, Koenraad De Bosschere
Workload Design: Selecting Representative Program-Input Pairs. [Citation Graph (0, 0)][DBLP] IEEE PACT, 2002, pp:83-94 [Conf]
- Hans Vandierendonck, Philippe Manet, Thibault Delavallee, Igor Loiselle, Jean-Didier Legat
By-passing the out-of-order execution pipeline to increase energy-efficiency. [Citation Graph (0, 0)][DBLP] Conf. Computing Frontiers, 2007, pp:97-104 [Conf]
- Hans Vandierendonck, Philippe Manet, Jean-Didier Legat
Application-specific reconfigurable XOR-indexing to eliminate cache conflict misses. [Citation Graph (0, 0)][DBLP] DATE, 2006, pp:357-362 [Conf]
- Hans Vandierendonck, Hans Logie, Koenraad De Bosschere
Trace Substitution. [Citation Graph (0, 0)][DBLP] Euro-Par, 2003, pp:556-565 [Conf]
- Hans Vandierendonck, Alex Ramírez, Koenraad De Bosschere, Mateo Valero
A Comparative Study of Redundancy in Trace Caches (Research Note). [Citation Graph (0, 0)][DBLP] Euro-Par, 2002, pp:512-516 [Conf]
- Bart Goeman, Hans Vandierendonck, Koenraad De Bosschere
Differential FCM: Increasing Value Prediction Accuracy by Improving Table Usage Efficiency. [Citation Graph (0, 0)][DBLP] HPCA, 2001, pp:207-0 [Conf]
- Henk Neefs, Hans Vandierendonck, Koenraad De Bosschere
A Technique for High Bandwidth and Deterministic Low Latency Load/Store Accesses to Multiple Cache Banks. [Citation Graph (0, 0)][DBLP] HPCA, 2000, pp:313-324 [Conf]
- Joshua J. Yi, Hans Vandierendonck, Lieven Eeckhout, David J. Lilja
The exigency of benchmark and compiler drift: designing tomorrow's processors with yesterday's tools. [Citation Graph (0, 0)][DBLP] ICS, 2006, pp:75-86 [Conf]
- Hans Vandierendonck, Koenraad De Bosschere
A Comparison of Locality-Based and Recency-Based Replacement Policies. [Citation Graph (0, 0)][DBLP] ISHPC, 2000, pp:310-318 [Conf]
- Hans Vandierendonck, Koen De Bosschere
Eccentric and fragile benchmarks. [Citation Graph (0, 0)][DBLP] ISPASS, 2004, pp:2-11 [Conf]
- Bjorn De Sutter, Hans Vandierendonck, Bruno De Bus, Koenraad De Bosschere
On the side-effects of code abstraction. [Citation Graph (0, 0)][DBLP] LCTES, 2003, pp:244-253 [Conf]
- Hans Vandierendonck, Koen De Bosschere
On the Impact of OS and Linker Effects on Level-2 Cache Performance. [Citation Graph (0, 0)][DBLP] MASCOTS, 2006, pp:87-95 [Conf]
- Hans Vandierendonck, Pedro Trancoso
Building and Validating a Reduced TPC-H Benchmark. [Citation Graph (0, 0)][DBLP] MASCOTS, 2006, pp:383-392 [Conf]
- Hans Vandierendonck, Koenraad De Bosschere
Trade-offs for Skewed-Associative Caches. [Citation Graph (0, 0)][DBLP] PARCO, 2003, pp:465-474 [Conf]
- Pedro Trancoso, Christodoulos Adamou, Hans Vandierendonck
Reducing TPC-H Benchmarking Time. [Citation Graph (0, 0)][DBLP] Panhellenic Conference on Informatics, 2005, pp:641-650 [Conf]
- Hans Vandierendonck, Koenraad De Bosschere
An Address Transformation Combining Block- and Word-Interleaving. [Citation Graph (0, 0)][DBLP] Computer Architecture Letters, 2002, v:1, n:, pp:- [Journal]
- Hans Vandierendonck, Koen De Bosschere
On Generating Set Index Functions for Randomized Caches. [Citation Graph (0, 0)][DBLP] Comput. J., 2004, v:47, n:2, pp:245-258 [Journal]
- Lieven Eeckhout, Hans Vandierendonck, Koenraad De Bosschere
Designing Computer Architecture Research Workloads. [Citation Graph (0, 0)][DBLP] IEEE Computer, 2003, v:36, n:2, pp:65-71 [Journal]
- Lieven Eeckhout, Hans Vandierendonck, Koenraad De Bosschere
Quantifying the Impact of Input Data Sets on Program Behavior and its Applications. [Citation Graph (0, 0)][DBLP] J. Instruction-Level Parallelism, 2003, v:5, n:, pp:- [Journal]
- Hans Vandierendonck, Koen De Bosschere
Highly accurate and efficient evaluation of randomising set index functions. [Citation Graph (0, 0)][DBLP] Journal of Systems Architecture, 2003, v:48, n:13-15, pp:429-452 [Journal]
- Hans Vandierendonck, Koenraad De Bosschere
XOR-Based Hash Functions. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 2005, v:54, n:7, pp:800-812 [Journal]
- Veerle Desmet, Hans Vandierendonck, Koen De Bosschere
Clustered indexing for branch predictors. [Citation Graph (0, 0)][DBLP] Microprocessors and Microsystems, 2007, v:31, n:3, pp:168-177 [Journal]
- Hans Vandierendonck, André Seznec
Fetch Gating Control Through Speculative Instruction Window Weighting. [Citation Graph (0, 0)][DBLP] HiPEAC, 2007, pp:120-135 [Conf]
Constructing Optimal XOR-Functions to Minimize Cache Conflict Misses. [Citation Graph (, )][DBLP]
Towards automatic program partitioning. [Citation Graph (, )][DBLP]
Experiences with Parallelizing a Bio-informatics Program on the Cell BE. [Citation Graph (, )][DBLP]
Extracting coarse-grain parallelism in general-purpose programs. [Citation Graph (, )][DBLP]
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