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Alexandre E. Eichenberger: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Alexandre E. Eichenberger, S. M. Lobo
    Efficient Edge Profiling for ILP-Processors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1998, pp:294-0 [Conf]
  2. Alexandre E. Eichenberger, Kathryn M. O'Brien, Kevin O'Brien, Peng Wu, Tong Chen, Peter H. Oden, Daniel A. Prener, Janice C. Shepherd, Byoungro So, Zehra Sura, Amy Wang, Tao Zhang, Peng Zhao, Michael Gschwind
    Optimizing Compiler for the CELL Processor. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2005, pp:161-172 [Conf]
  3. Peng Wu, Alexandre E. Eichenberger, Amy Wang
    Efficient SIMD Code Generation for Runtime Alignment and Length Conversion. [Citation Graph (0, 0)][DBLP]
    CGO, 2005, pp:153-164 [Conf]
  4. Alexandre E. Eichenberger, Santosh G. Abraham
    Modeling load imbalance and fuzzy barriers for scalable shared-memory multiprocessors. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1995, pp:262-271 [Conf]
  5. Ivan D. Baev, Waleed Meleis, Alexandre E. Eichenberger
    Lower Bounds on Precedence-Constrained Scheduling for Parallel Processors. [Citation Graph (0, 0)][DBLP]
    ICPP, 2000, pp:549-554 [Conf]
  6. Alexandre E. Eichenberger, Santosh G. Abraham
    Impact of Load Imbalance on the Design of Software Barriers. [Citation Graph (0, 0)][DBLP]
    ICPP (2), 1995, pp:63-72 [Conf]
  7. Alexandre E. Eichenberger, Edward S. Davidson, Santosh G. Abraham
    Optimum Modulo Schedules for Minimum Register Requirements. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1995, pp:31-40 [Conf]
  8. Peng Wu, Alexandre E. Eichenberger, Amy Wang, Peng Zhao
    An integrated simdization framework using virtual vectors. [Citation Graph (0, 0)][DBLP]
    ICS, 2005, pp:169-178 [Conf]
  9. Alexandre E. Eichenberger, Edward S. Davidson
    Register allocation for predicated code. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:180-191 [Conf]
  10. Alexandre E. Eichenberger, Edward S. Davidson
    Stage scheduling: a technique to reduce the register requirements of a modulo schedule. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:338-349 [Conf]
  11. Alexandre E. Eichenberger, Edward S. Davidson, Santosh G. Abraham
    Minimum register requirements for a modulo schedule. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:75-84 [Conf]
  12. Alexandre E. Eichenberger, Waleed Meleis
    Balance Scheduling: Weighting Branch Tradeoffs in Superblocks. [Citation Graph (0, 0)][DBLP]
    MICRO, 1999, pp:272-283 [Conf]
  13. Alexandre E. Eichenberger, Waleed Meleis, Suman Maradani
    An integrated approach to accelerate data and predicate computations in hyperblocks. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:101-111 [Conf]
  14. Erik Nystrom, Alexandre E. Eichenberger
    Effective Cluster Assignment for Modulo Scheduling. [Citation Graph (0, 0)][DBLP]
    MICRO, 1998, pp:103-114 [Conf]
  15. Alexandre E. Eichenberger, Edward S. Davidson
    A Reduced Multipipeline Machine Description that Preserves Scheduling Constraints. [Citation Graph (0, 0)][DBLP]
    PLDI, 1996, pp:12-22 [Conf]
  16. Alexandre E. Eichenberger, Edward S. Davidson
    Efficient Formulation for Optimal Modulo Schedulers. [Citation Graph (0, 0)][DBLP]
    PLDI, 1997, pp:194-205 [Conf]
  17. Alexandre E. Eichenberger, Peng Wu, Kevin O'Brien
    Vectorization for SIMD architectures with alignment constraints. [Citation Graph (0, 0)][DBLP]
    PLDI, 2004, pp:82-93 [Conf]
  18. Ivan D. Baev, Waleed Meleis, Alexandre E. Eichenberger
    Algorithms for Total Weighted Completion Time Scheduling. [Citation Graph (0, 0)][DBLP]
    SODA, 1999, pp:852-853 [Conf]
  19. Ivan D. Baev, Waleed Meleis, Alexandre E. Eichenberger
    An Experimental Study of Algorithms for Weighted Completion Time Scheduling. [Citation Graph (0, 0)][DBLP]
    Algorithmica, 2002, v:33, n:1, pp:34-51 [Journal]
  20. Alexandre E. Eichenberger, Kevin O'Brien, Kathryn M. O'Brien, Peng Wu, Tong Chen, Peter H. Oden, Daniel A. Prener, Janice C. Shepherd, Byoungro So, Zehra Sura, Amy Wang, Tao Zhang, Peng Zhao, Michael Gschwind, Roch Archambault, Yaoqing Gao, Roland Koo
    Using advanced compiler technology to exploit the performance of the Cell Broadband EngineTM architecture. [Citation Graph (0, 0)][DBLP]
    IBM Systems Journal, 2006, v:45, n:1, pp:59-84 [Journal]
  21. Ivan D. Baev, Waleed Meleis, Alexandre E. Eichenberger
    Lower bounds on precedence-constrained scheduling for parallel processors. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 2002, v:83, n:1, pp:27-32 [Journal]
  22. Waleed Meleis, Alexandre E. Eichenberger, Ivan D. Baev
    Scheduling Superblocks with Bound-Based Branch Trade-Offs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:8, pp:784-797 [Journal]

  23. Exploiting Parallelism with Dependence-Aware Scheduling. [Citation Graph (, )][DBLP]


  24. Hybrid access-specific software cache techniques for the cell BE architecture. [Citation Graph (, )][DBLP]


  25. Automatic creation of tile size selection models. [Citation Graph (, )][DBLP]


  26. Compact multi-dimensional kernel extraction for register tiling. [Citation Graph (, )][DBLP]


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