Search the dblp DataBase

Publications of Author

1. Wei-Yu Chen, Costin Iancu, Katherine A. Yelick
   Communication Optimizations for Fine-Grained UPC Applications. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2005, pp:267-278 [Conf]
   
2. Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer
   Test generation for crosstalk-induced faults: framework and computational result. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2000, pp:305-310 [Conf]
   
3. Cheng Wang, Wei-Yu Chen, Youfeng Wu, Bratin Saha, Ali-Reza Adl-Tabatabai
   Code Generation and Optimization for Transactional Memory Constructs in an Unmanaged Language. [Citation Graph (0, 0)][DBLP]
   CGO, 2007, pp:34-48 [Conf]
   
4. Amitava Majumdar, Wei-Yu Chen, Jun Guo
   Hold time validation on silicon and the relevance of hazards in timing analysis. [Citation Graph (0, 0)][DBLP]
   DAC, 2006, pp:326-331 [Conf]
   
5. Christian Bell, Wei-Yu Chen, Dan Bonachea, Katherine A. Yelick
   Evaluating support for global address space languages on the Cray X1. [Citation Graph (0, 0)][DBLP]
   ICS, 2004, pp:184-195 [Conf]
   
6. Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer
   Test generation for crosstalk-induced delay in integrated circuits. [Citation Graph (0, 0)][DBLP]
   ITC, 1999, pp:191-200 [Conf]
   
7. Wei-Yu Chen, Arvind Krishnamurthy, Katherine A. Yelick
   Polynomial-Time Algorithms for Enforcing Sequential Consistency in SPMD Programs with Arrays. [Citation Graph (0, 0)][DBLP]
   LCPC, 2003, pp:340-356 [Conf]
   
8. Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer
   Analytical models for crosstalk excitation and propagation in VLSI circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1117-1131 [Journal]
   
9. Wei-Yu Chen, Dan Bonachea, Costin Iancu, Katherine A. Yelick
   Automatic nonblocking communication for partitioned global address space programs. [Citation Graph (0, 0)][DBLP]
   ICS, 2007, pp:158-167 [Conf]
   
10. 
    A technique for selecting CMOS transistor orders. [Citation Graph (, )][DBLP]
    
    
11. 
    An efficient gate delay model for VLSI design. [Citation Graph (, )][DBLP]
    
    
12. 
    Productivity and performance using partitioned global address space languages. [Citation Graph (, )][DBLP]
    
    
13. 
    Ubiquitous e-Helpers: An UPnP-based home automation platform. [Citation Graph (, )][DBLP]
    
    
14. 
    The effectiveness of the handheld devices based on mobiles learning. [Citation Graph (, )][DBLP]
    
    
15. 
    The Creative Commons Based Digital Right Management Model. [Citation Graph (, )][DBLP]
    
    
16. 
    Role-Based Access Control of Digital Right Management. [Citation Graph (, )][DBLP]