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Tor M. Aamodt :
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Tor M. Aamodt , Paul Chow Embedded ISA support for enhanced floating-point to fixed-point ANSI-C compilation. [Citation Graph (0, 0)][DBLP ] CASES, 2000, pp:128-137 [Conf ] Tor M. Aamodt , Paul Chow , Per Hammarlund , Hong Wang , John Paul Shen Hardware Support for Prescient Instruction Prefetch. [Citation Graph (0, 0)][DBLP ] HPCA, 2004, pp:84-95 [Conf ] Tor M. Aamodt , Pedro Marcuello , Paul Chow , Antonio González , Per Hammarlund , Hong Wang , John Paul Shen A framework for modeling and optimization of prescient instruction prefetch. [Citation Graph (0, 0)][DBLP ] SIGMETRICS, 2003, pp:13-24 [Conf ] Tor M. Aamodt , Paul Chow Optimization of data prefetch helper threads with path-expression based statistical modeling. [Citation Graph (0, 0)][DBLP ] ICS, 2007, pp:210-221 [Conf ] Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor. [Citation Graph (, )][DBLP ] A first-order fine-grained multithreaded throughput model. [Citation Graph (, )][DBLP ] Analyzing CUDA workloads using a detailed GPU simulator. [Citation Graph (, )][DBLP ] Visualizing complex dynamics in many-core accelerator architectures. [Citation Graph (, )][DBLP ] Accelerating trace computation in post-silicon debug. [Citation Graph (, )][DBLP ] Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow. [Citation Graph (, )][DBLP ] Complexity effective memory access scheduling for many-core accelerator architectures. [Citation Graph (, )][DBLP ] Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs. [Citation Graph (, )][DBLP ] Search in 0.001secs, Finished in 0.002secs