The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Tor M. Aamodt: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Tor M. Aamodt, Paul Chow
    Embedded ISA support for enhanced floating-point to fixed-point ANSI-C compilation. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:128-137 [Conf]
  2. Tor M. Aamodt, Paul Chow, Per Hammarlund, Hong Wang, John Paul Shen
    Hardware Support for Prescient Instruction Prefetch. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:84-95 [Conf]
  3. Tor M. Aamodt, Pedro Marcuello, Paul Chow, Antonio González, Per Hammarlund, Hong Wang, John Paul Shen
    A framework for modeling and optimization of prescient instruction prefetch. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 2003, pp:13-24 [Conf]
  4. Tor M. Aamodt, Paul Chow
    Optimization of data prefetch helper threads with path-expression based statistical modeling. [Citation Graph (0, 0)][DBLP]
    ICS, 2007, pp:210-221 [Conf]

  5. Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor. [Citation Graph (, )][DBLP]


  6. A first-order fine-grained multithreaded throughput model. [Citation Graph (, )][DBLP]


  7. Analyzing CUDA workloads using a detailed GPU simulator. [Citation Graph (, )][DBLP]


  8. Visualizing complex dynamics in many-core accelerator architectures. [Citation Graph (, )][DBLP]


  9. Accelerating trace computation in post-silicon debug. [Citation Graph (, )][DBLP]


  10. Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow. [Citation Graph (, )][DBLP]


  11. Complexity effective memory access scheduling for many-core accelerator architectures. [Citation Graph (, )][DBLP]


  12. Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs. [Citation Graph (, )][DBLP]


Search in 0.002secs, Finished in 0.002secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002