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Federico Angiolini: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Federico Angiolini, Luca Benini, Alberto Caprara
    Polynomial-time algorithm for on-chip scratchpad memory partitioning. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:318-326 [Conf]
  2. Federico Angiolini, Francesco Menichelli, Alberto Ferrero, Luca Benini, Mauro Olivieri
    A post-compiler approach to scratchpad mapping of code. [Citation Graph (0, 0)][DBLP]
    CASES, 2004, pp:259-267 [Conf]
  3. Federico Angiolini, Jianjiang Ceng, Rainer Leupers, Federico Ferrari, Cesare Ferri, Luca Benini
    An integrated open framework for heterogeneous MPSoC design space exploration. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1145-1150 [Conf]
  4. Federico Angiolini, Paolo Meloni, Salvatore Carta, Luca Benini, Luigi Raffo
    Contrasting a NoC and a traditional interconnect fabric with layout awareness. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:124-129 [Conf]
  5. Mirko Loghi, Federico Angiolini, Davide Bertozzi, Luca Benini, Roberto Zafalon
    Analyzing On-Chip Communication in a MPSoC Environment. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:752-757 [Conf]
  6. Shankar Mahadevan, Federico Angiolini, Michael Storgaard, Rasmus Grøndahl Olsen, Jens Sparsø, Jan Madsen
    A Network Traffic Generator Model for Fast Network-on-Chip Simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:780-785 [Conf]
  7. Stergios Stergiou, Federico Angiolini, Salvatore Carta, Luigi Raffo, Davide Bertozzi, Giovanni De Micheli
    ast pipes Lite: A Synthesis Oriented Design Library For Networks on Chips. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1188-1193 [Conf]
  8. Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo
    Designing application-specific networks on chips with floorplan information. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:355-362 [Conf]
  9. Federico Angiolini, Paolo Meloni, Luca Benini, Salvatore Carta, Luigi Raffo
    Networks on Chips: A Synthesis Perspective. [Citation Graph (0, 0)][DBLP]
    PARCO, 2005, pp:745-752 [Conf]
  10. Antonio Pullini, Federico Angiolini, Davide Bertozzi, Luca Benini
    Fault tolerance overhead in network-on-chip flow control schemes. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:224-229 [Conf]
  11. Federico Angiolini, Luca Benini, Alberto Caprara
    An efficient profile-based algorithm for scratchpad memory partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1660-1676 [Journal]
  12. Federico Angiolini, M. Haykel Ben Jamaa, David Atienza, Luca Benini, Giovanni De Micheli
    Interactive presentation: Improving the fault tolerance of nanometric PLA designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:570-575 [Conf]
  13. Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, Jan Madsen
    A Traffic Injection Methodology with Support for System-Level Synchronization. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:145-161 [Conf]
  14. Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo
    Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:158-163 [Conf]
  15. Antonio Pullini, Federico Angiolini, Paolo Meloni, David Atienza, Srinivasan Murali, Luigi Raffo, Giovanni De Micheli, Luca Benini
    NoC Design and Implementation in 65nm Technology. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:273-282 [Conf]
  16. Antonio Pullini, Federico Angiolini, Srinivasan Murali, David Atienza, Giovanni De Micheli, Luca Benini
    Bringing NoCs to 65 nm. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:5, pp:75-85 [Journal]

  17. Networks on Chips: from research to products. [Citation Graph (, )][DBLP]

  18. Developing Mesochronous Synchronizers to Enable 3D NoCs. [Citation Graph (, )][DBLP]

  19. Synthesis of low-overhead configurable source routing tables for network interfaces. [Citation Graph (, )][DBLP]

  20. A method for calculating hard QoS guarantees for Networks-on-Chip. [Citation Graph (, )][DBLP]

  21. Reliability Support for On-Chip Memories Using Networks-on-Chip. [Citation Graph (, )][DBLP]

  22. Automated Pathfinding tool chain for 3D-stacked integrated circuits: Practical case study. [Citation Graph (, )][DBLP]

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