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Robert A. Walker: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ken W. Batcher, Robert A. Walker
    Cluster miss prediction with prefetch on miss for embedded CPU instruction caches. [Citation Graph (0, 0)][DBLP]
    CASES, 2004, pp:24-34 [Conf]
  2. Donald E. Thomas, Elizabeth M. Dirkes, Robert A. Walker, Jayanth V. Rajan, John A. Nestor, Robert L. Blackburn
    The System Architect's Workbench. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:337-343 [Conf]
  3. Robert A. Walker, Donald E. Thomas
    A model of design representation and synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1985, pp:453-459 [Conf]
  4. Stephen A. Blythe, Robert A. Walker
    Efficiently Searching the Optimal Design Space. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:192-0 [Conf]
  5. Kenneth E. Batcher, Robert A. Walker
    Cluster miss prediction for instruction caches in embedded networking applications. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:358-363 [Conf]
  6. Samit Chaudhuri, Robert A. Walker
    Bounding Algorithms for Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:234-235 [Conf]
  7. Ching-Tang Chang, Kenneth Rose, Robert A. Walker
    Cluster-Oriented Scheduling in Pipelined Data Path Syntesis. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:374-378 [Conf]
  8. Samit Chaudhuri, Robert A. Walker, John Mitchell
    The Structure of Assignment, Precedence, and Resource Constraints in the ILP Approach to the Scheduling Problem. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:25-29 [Conf]
  9. Robert A. Walker, Jerry L. Potter, Yanping Wang, Meiduo Wu
    Implementing Associative Processing: Rethinking EarlierArchitectural Decisions. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2001, pp:195- [Conf]
  10. Hong Wang, Robert A. Walker
    Implementing a Scalable ASC Processor. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:267- [Conf]
  11. Hong Wang, Lei Xie, Meiduo Wu, Robert A. Walker
    A Scalable Associative Processor with Applications in Database and Image Processing. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  12. Meiduo Wu, Robert A. Walker, Jerry L. Potter
    Implementing Associative Search and Responder Resolution. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  13. Stephen A. Blythe, Robert A. Walker
    Toward a Practical Methodology for Completely Characterizing the Optimal Design Space. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:8-13 [Conf]
  14. Samit Chaudhuri, Stephen A. Blythe, Robert A. Walker
    An exact methodology for scheduling in a 3D design space. [Citation Graph (0, 0)][DBLP]
    ISSS, 1995, pp:78-83 [Conf]
  15. Robert A. Walker, Shivkumar Ramabadran, Rajive Joshi, Steinar Flatland
    Increasing User Interaction During High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    MICRO, 1991, pp:133-142 [Conf]
  16. Hong Wang, Robert A. Walker
    A Scalable Pipelined Associative SIMD Array with Reconfigurable PE Interconnection Network for Embedded Applications. [Citation Graph (0, 0)][DBLP]
    IASTED PDCS, 2005, pp:667-673 [Conf]
  17. Ken W. Batcher, Robert A. Walker
    Interrupt Triggered Software Prefetching for Embedded CPU Instruction Cache. [Citation Graph (0, 0)][DBLP]
    IEEE Real Time Technology and Applications Symposium, 2006, pp:91-102 [Conf]
  18. Robert A. Walker
    A practical one-semester "VLSI design" course for computer science (and other) majors. [Citation Graph (0, 0)][DBLP]
    SIGCSE, 1999, pp:237-241 [Conf]
  19. Samit Chaudhuri, Robert A. Walker
    ILP-Based Scheduling with Time and Resource Constraints in High Level Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:17-20 [Conf]
  20. Donald E. Thomas, Charles Y. Hitchcock III, Thaddeus J. Kowalski, Jayanth V. Rajan, Robert A. Walker
    Automatic Data Path Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1983, v:16, n:12, pp:59-70 [Journal]
  21. Charles J. Colbourn, Sosina Martirosyan, Tran van Trung, Robert A. Walker
    Roux-type constructions for covering arrays of strengths three and four. [Citation Graph (0, 0)][DBLP]
    Des. Codes Cryptography, 2006, v:41, n:1, pp:33-57 [Journal]
  22. Robert A. Walker
    Guest Editor's Introduction: The Status of High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1994, v:11, n:4, pp:42-43 [Journal]
  23. Robert A. Walker, Samit Chaudhuri
    Introduction to the Scheduling Problem. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1995, v:12, n:2, pp:60-69 [Journal]
  24. Robert A. Walker, Donald E. Thomas
    Behavioral transformation for algorithmic level IC design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:10, pp:1115-1128 [Journal]
  25. Stephen A. Blythe, Robert A. Walker
    Efficient optimal design space characterization methodologies. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:322-336 [Journal]
  26. Kevin Schaffer, Robert A. Walker
    A Prototype Multithreaded Associative SIMD Processor. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-6 [Conf]
  27. Samit Chaudhuri, Robert A. Walker, J. E. Mitchell
    Analyzing and exploiting the structure of the constraints in the ILP approach to the scheduling problem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:456-471 [Journal]
  28. Samit Chaudhuri, S. A. Blthye, Robert A. Walker
    A solution methodology for exact design space exploration in a three-dimensional design space. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:1, pp:69-81 [Journal]
  29. Samit Chaudhuri, Robert A. Walker
    Computing lower bounds on functional units before scheduling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:2, pp:273-279 [Journal]

  30. Dynamic Round-Robin Task Scheduling to Reduce Cache Misses for Embedded Systems. [Citation Graph (, )][DBLP]


  31. Using hardware multithreading to overcome broadcast/reduction latency in an associative SIMD processor. [Citation Graph (, )][DBLP]


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