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Jaime H. Moreno:
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Publications of Author
- Hillery C. Hunter, Jaime H. Moreno
A new look at exploiting data parallelism in embedded systems. [Citation Graph (0, 0)][DBLP] CASES, 2003, pp:159-169 [Conf]
- Victor V. Zyuban, Sameh W. Asaad, Thomas W. Fox, Anne-Marie Haen, Daniel Littrell, Jaime H. Moreno
Design methodology for semi custom processor cores. [Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2004, pp:448-452 [Conf]
- Jaime H. Moreno, Tomás Lang
Replication and Pipelining in Multiple-Instance Algorithms. [Citation Graph (0, 0)][DBLP] ICPP, 1986, pp:285-292 [Conf]
- Jaime H. Moreno, Tomás Lang
Graph-based Partitioning of Matrix Algorithms for Systolic Arrays: Application to Transitive Closure. [Citation Graph (0, 0)][DBLP] ICPP (1), 1988, pp:28-31 [Conf]
- Jaime H. Moreno, Mayan Moudgil
Scalable Instruction-Level Parallelism Through Tree-Instructions. [Citation Graph (0, 0)][DBLP] International Conference on Supercomputing, 1997, pp:1-11 [Conf]
- Jude A. Rivers, Sameh W. Asaad, John-David Wellman, Jaime H. Moreno
Reducing instruction fetch energy with backwards branch control information and buffering. [Citation Graph (0, 0)][DBLP] ISLPED, 2003, pp:322-325 [Conf]
- Jaime H. Moreno
Chip-level integration: the new frontier for microprocessor architecture. [Citation Graph (0, 0)][DBLP] SPAA, 2006, pp:328- [Conf]
- Jaime H. Moreno, Tomás Lang
Matric Computations on Systolic-Type Meshes. [Citation Graph (0, 0)][DBLP] IEEE Computer, 1990, v:23, n:4, pp:32-51 [Journal]
- Jaime H. Moreno, Victor V. Zyuban, Uzi Shvadron, Fredy D. Neeser, Jeff H. Derby, Malcolm S. Ware, Krishnan Kailas, Ayal Zaks, Amir B. Geva, Shay Ben-David, Sameh W. Asaad, Thomas W. Fox, Daniel Littrell, Marina Biberstein, Dorit Naishlos, Hillery C. Hunter
An innovative low-power high-performance programmable signal processor for digital communications. [Citation Graph (0, 0)][DBLP] IBM Journal of Research and Development, 2003, v:47, n:2-3, pp:299-326 [Journal]
- Mayan Moudgill, P. Bose, J. H. Moreno
Validation of Turandot, a fast processor model for microarchitecture exploration. [Citation Graph (0, 0)][DBLP] IPCCC, 1999, pp:451-457 [Conf]
True value: assessing and optimizing the cost of computing at the data center level. [Citation Graph (, )][DBLP]
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