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Cristina Silvano: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Giovanni Beltrame, Gianluca Palermo, Donatella Sciuto, Cristina Silvano
    Plug-in of power models in the StepNP exploration platform: analysis of power/performance trade-offs. [Citation Graph (0, 0)][DBLP]
    CASES, 2004, pp:85-92 [Conf]
  2. William Fornaciari, M. Polentarutti, Donatella Sciuto, Cristina Silvano
    Power optimization of system-level address buses based on software profiling. [Citation Graph (0, 0)][DBLP]
    CODES, 2000, pp:29-33 [Conf]
  3. William Fornaciari, Donatella Sciuto, Cristina Silvano
    Power estimation for architectural exploration of HW/SW communication on system-level buses. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:152-156 [Conf]
  4. William Fornaciari, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria
    A design framework to efficiently explore energy-delay tradeoffs. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:260-265 [Conf]
  5. Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria
    Instruction-level power estimation for embedded VLIW cores. [Citation Graph (0, 0)][DBLP]
    CODES, 2000, pp:34-38 [Conf]
  6. Giovanni Beltrame, Dario Bruschi, Donatella Sciuto, Cristina Silvano
    Decision-theoretic exploration of multiProcessor platforms. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:205-210 [Conf]
  7. Andrea Bona, Mariagiovanna Sami, Donatella Sciuto, Vittorio Zaccaria, Cristina Silvano, Roberto Zafalon
    Energy estimation and optimization of embedded VLIW processors based on instruction clustering. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:886-891 [Conf]
  8. Giovanni Beltrame, Donatella Sciuto, Cristina Silvano, Damien Lyonnard, Chuck Pilkington
    Exploiting TLM and object introspection for system-level simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:100-105 [Conf]
  9. Luca Benini, Giovanni De Micheli, Donatella Sciuto, Enrico Macii, Cristina Silvano
    Address Bus Encoding Techniques for System-Level Power Optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:861-0 [Conf]
  10. Andrea Bona, Mariagiovanna Sami, Donatella Sciuto, Vittorio Zaccaria, Cristina Silvano, Roberto Zafalon
    An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1128- [Conf]
  11. William Fornaciari, Donatella Sciuto, Cristina Silvano
    Influence of Caching and Encoding on Power Dissipation of System-Level Buses for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:762-763 [Conf]
  12. Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa
    Power/performance hardware optimization for synchronization intensive applications in MPSoCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:606-611 [Conf]
  13. Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria
    Power-Performance System-Level Exploration of a MicroSPARC2-Based Embedded Architecture. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:20182-20187 [Conf]
  14. Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon
    Exploiting data forwarding to reduce the power budget of VLIW embedded processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:252-257 [Conf]
  15. Donatella Sciuto, Cristina Silvano, Renato Stefanelli
    Systematic AUED Codes for Self-Checking Architectures. [Citation Graph (0, 0)][DBLP]
    DFT, 1998, pp:183-191 [Conf]
  16. Luca Benini, Giovanni De Micheli, Enrico Macii, Donatella Sciuto, Cristina Silvano
    Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1997, pp:77-82 [Conf]
  17. Matteo Monchiero, Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon
    Power-aware branch prediction techniques: a compiler-hints based approach for VLIW processors. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:440-443 [Conf]
  18. Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon
    Branch prediction techniques for low-power VLIW processors. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:225-228 [Conf]
  19. Gianluca Palermo, Cristina Silvano, S. Valsecchi, Vittorio Zaccaria
    A system-level methodology for fast multi-objective design space exploration. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:92-95 [Conf]
  20. Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria
    Power Exploration for Embedded VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:498-503 [Conf]
  21. William Fornaciari, Donatella Sciuto, Cristina Silvano
    Power Estimation of System-Level Buses for Microprocessor-Based Architectures: A Case Study. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:131-0 [Conf]
  22. Luca Penzo, Donatella Sciuto, Cristina Silvano
    GECO: A Tool for Automatic Generation of Error Control Codes for Computer Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:912-915 [Conf]
  23. William Fornaciari, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria
    Fast system-level exploration of memory architectures driven by energy-delay metrics. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:502-505 [Conf]
  24. Nicola Dragone, Roberto Zafalon, Carlo Guardiani, Cristina Silvano
    Power invariant vector compaction based on bit clustering and temporal partitioning. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:118-120 [Conf]
  25. Gianluca Palermo, Cristina Silvano
    PIRATE: A Framework for Power/Performance Exploration of Network-on-Chip Architectures. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:521-531 [Conf]
  26. Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria
    A Flexible Framework for Fast Multi-objective Design Space Exploration of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:249-258 [Conf]
  27. Giovanni Agosta, Gianluca Palermo, Cristina Silvano
    Multi-objective co-exploration of source code transformations and design space architectures for low-power embedded systems. [Citation Graph (0, 0)][DBLP]
    SAC, 2004, pp:891-896 [Conf]
  28. Lorenzo Salvemini, Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon
    A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    SAC, 2003, pp:672-678 [Conf]
  29. Luca Penzo, Donatella Sciuto, Cristina Silvano
    VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:156-160 [Conf]
  30. Matteo Monchiero, Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon
    Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach. [Citation Graph (0, 0)][DBLP]
    Integration, 2005, v:38, n:3, pp:515-524 [Journal]
  31. Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria
    An instruction-level energy model for embedded VLIW architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:9, pp:998-1010 [Journal]
  32. Luca Penzo, Donatella Sciuto, Cristina Silvano
    Construction techniques for systematic SEC-DED codes with single byte error detection and partial correction capability for computer memory systems. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Information Theory, 1995, v:41, n:2, pp:584-591 [Journal]
  33. Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa
    Efficient Synchronization for Embedded On-Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:10, pp:1049-1062 [Journal]
  34. Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa
    Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:144-151 [Conf]
  35. Giovanni Beltrame, Donatella Sciuto, Cristina Silvano, Pierre G. Paulin, Essaid Bensoudane
    An Application Mapping Methodology and Case Study for Multi-Processor On-Chip Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:146-151 [Conf]
  36. Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa
    Exploration of distributed shared memory architectures for NoC-based multiprocessors. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:10, pp:719-732 [Journal]
  37. William Fornaciari, P. Gubian, Donatella Sciuto, Cristina Silvano
    Power estimation of embedded systems: a hardware/software codesign approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:266-275 [Journal]
  38. Franco Fummi, Donatella Sciuto, Cristina Silvano
    Automatic generation of error control codes for computer applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:502-506 [Journal]
  39. Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon
    Low-power data forwarding for VLIW embedded architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:5, pp:614-622 [Journal]

  40. Mapping and Topology Customization Approaches for Application-Specific STNoC Designs. [Citation Graph (, )][DBLP]


  41. Variability-aware robust design space exploration of chip multiprocessor architectures. [Citation Graph (, )][DBLP]


  42. Efficiency and scalability of barrier synchronization on NoC based many-core architectures. [Citation Graph (, )][DBLP]


  43. A data protection unit for NoC-based architectures. [Citation Graph (, )][DBLP]


  44. A security monitoring service for NoCs. [Citation Graph (, )][DBLP]


  45. A correlation-based design space exploration methodology for multi-processor systems-on-chip. [Citation Graph (, )][DBLP]


  46. MPSoCs run-time monitoring through Networks-on-Chip. [Citation Graph (, )][DBLP]


  47. An industrial design space exploration framework for supporting run-time resource management on multi-core systems. [Citation Graph (, )][DBLP]


  48. Energy-performance design space exploration in SMT architectures exploiting selective load value predictions. [Citation Graph (, )][DBLP]


  49. Application-Specific Topology Design Customization for STNoC. [Citation Graph (, )][DBLP]


  50. Security Aspects in Networks-on-Chips: Overview and Proposals for Secure Implementations. [Citation Graph (, )][DBLP]


  51. A Modular Approach to Model Heterogeneous MPSoC at Cycle Level. [Citation Graph (, )][DBLP]


  52. Discrete Particle Swarm Optimization for Multi-objective Design Space Exploration. [Citation Graph (, )][DBLP]


  53. Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip. [Citation Graph (, )][DBLP]


  54. Robust optimization of SoC architectures: A multi-scenario approach. [Citation Graph (, )][DBLP]


  55. Dynamic configuration of application-specific implicit instructions for embedded pipelined processors. [Citation Graph (, )][DBLP]


  56. An efficient design space exploration methodology for multiprocessor SoC architectures based on response surface methods. [Citation Graph (, )][DBLP]


  57. Multi-processor system-on-chip Design Space Exploration based on multi-level modeling techniques. [Citation Graph (, )][DBLP]


  58. An Efficient Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints. [Citation Graph (, )][DBLP]


  59. A design space exploration methodology supporting run-time resource management for multi-processor Systems-on-chip. [Citation Graph (, )][DBLP]


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