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John Lach: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Zhijian Lu, Jason Hein, Marty Humphrey, Mircea R. Stan, John Lach, Kevin Skadron
    Control-theoretic dynamic frequency and voltage scaling for multimedia workloads. [Citation Graph (0, 0)][DBLP]
    CASES, 2002, pp:156-163 [Conf]
  2. Vinu Vijay Kumar, John Lach
    Highly flexible multi-mode system synthesis. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:27-32 [Conf]
  3. Andrew B. Kahng, John Lach, William H. Mangione-Smith, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe
    Watermarking Techniques for Intellectual Property Protection. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:776-781 [Conf]
  4. John Lach, William H. Mangione-Smith, Miodrag Potkonjak
    Efficient error detection, localization, and correction for FPGA-based debugging. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:207-212 [Conf]
  5. John Lach, William H. Mangione-Smith, Miodrag Potkonjak
    Robust FPGA Intellectual Property Protection Through Multiple Small Watermarks. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:831-836 [Conf]
  6. Yan Zhang, Zhijian Lu, John Lach, Kevin Skadron, Mircea R. Stan
    Optimal procrastinating voltage scheduling for hard real-time systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:905-908 [Conf]
  7. Zhijian Lu, Yan Zhang, Mircea R. Stan, John Lach, Kevin Skadron
    Procrastinating voltage scheduling with discrete frequency sets. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:456-461 [Conf]
  8. Vinu Vijay Kumar, John Lach
    Fine-Grained Self-Healing Hardware for Large-Scale Autonomic Systems. [Citation Graph (0, 0)][DBLP]
    DEXA Workshops, 2003, pp:707-712 [Conf]
  9. Vinu Vijay Kumar, John Lach
    Heterogeneous Redundancy for Fault and Defect Tolerance with Complexity Independent Area Overhead. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:571-0 [Conf]
  10. John Lach, William H. Mangione-Smith, Miodrag Potkonjak
    Algorithms for Efficient Runtime Fault Recovery on Diverse FPGA Architectures. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:386-394 [Conf]
  11. Vinu Vijay Kumar, Rashi Verma, John Lach, Joanne Bechta Dugan
    A Markov Reward Model for Reliable Synchronous Dataflow System Design. [Citation Graph (0, 0)][DBLP]
    DSN, 2004, pp:817-825 [Conf]
  12. John Lach, William H. Mangione-Smith, Miodrag Potkonjak
    Efficiently Supporting Fault-Tolerance in FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1998, pp:105-115 [Conf]
  13. John Lach, William H. Mangione-Smith, Miodrag Potkonjak
    Efficient Support of Hardware Debugging Through FPGA Physical Design Partitioning. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:247- [Conf]
  14. Vinu Vijay Kumar, John Lach
    Designing, Scheduling, and Allocating Flexible Arithmetic Components. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1166-1169 [Conf]
  15. Nadine Gergel, Shana Craft, John Lach
    Modeling QCA for area minimization in logic synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:60-63 [Conf]
  16. John Lach, William H. Mangione-Smith, Miodrag Potkonjak
    Signature hiding techniques for FPGA intellectual property protection. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:186-189 [Conf]
  17. Zhijian Lu, Wei Huang, John Lach, Mircea R. Stan, Kevin Skadron
    Interconnect lifetime prediction under dynamic stress for reliability-aware design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:327-334 [Conf]
  18. John Lach, Jason Brandon, Kevin Skadron
    A General Post-Processing Approach to Leakage Current Reduction in SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:144-150 [Conf]
  19. Zhijian Lu, John Lach, Mircea R. Stan, Kevin Skadron
    Reducing Multimedia Decode Power using Feedback Control. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:489-0 [Conf]
  20. Sivakumar Velusamy, Wei Huang, John Lach, Mircea R. Stan, Kevin Skadron
    Monitoring Temperature in FPGA based SoCs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:634-640 [Conf]
  21. John Lach, William H. Mangione-Smith, Miodrag Potkonjak
    Fingerprinting Digital Circuits on Programmable Hardware. [Citation Graph (0, 0)][DBLP]
    Information Hiding, 1998, pp:16-31 [Conf]
  22. John Lach, William H. Mangione-Smith, Miodrag Potkonjak
    Enhanced Intellectual Property Protection for Digital Circuits on Programmable Hardware. [Citation Graph (0, 0)][DBLP]
    Information Hiding, 1999, pp:286-301 [Conf]
  23. Yan Zhang, John Lach, Kevin Skadron, Mircea R. Stan
    Odd/even bus invert with two-phase transfer for buses with coupling. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:80-83 [Conf]
  24. Zhijian Lu, John Lach, Mircea R. Stan, Kevin Skadron
    Alloyed Branch History: Combining Global and Local Branch History for Robust Performance. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2003, v:31, n:2, pp:137-177 [Journal]
  25. Zhijian Lu, John Lach, Mircea R. Stan, Kevin Skadron
    Improved Thermal Management with Reliability Banking. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:6, pp:40-49 [Journal]
  26. Andrew B. Kahng, John Lach, William H. Mangione-Smith, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe
    Constraint-based watermarking techniques for design IP protection. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:10, pp:1236-1252 [Journal]
  27. John Lach, William H. Mangione-Smith, Miodrag Potkonjak
    Fingerprinting techniques for field-programmable gate arrayintellectual property protection. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:10, pp:1253-1261 [Journal]
  28. John Lach, Kia Bazargan
    Editorial: Special issue on dynamically adaptable embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2004, v:3, n:2, pp:233-236 [Journal]
  29. Zhijian Lu, Wei Huang, Mircea R. Stan, Kevin Skadron, John Lach
    Interconnect Lifetime Prediction for Reliability-Aware Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:2, pp:159-172 [Journal]
  30. John Lach, William H. Mangione-Smith, Miodrag Potkonjak
    Low overhead fault-tolerant FPGA systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:212-221 [Journal]

  31. Negative-skewed shadow registers for at-speed delay variation characterization. [Citation Graph (, )][DBLP]


  32. Power switch characterization for fine-grained dynamic voltage scaling. [Citation Graph (, )][DBLP]


  33. Neural Network Gait Classification for On-Body Inertial Sensors. [Citation Graph (, )][DBLP]


  34. Accurate, Fast Fall Detection Using Gyroscopes and Accelerometer-Derived Posture Information. [Citation Graph (, )][DBLP]


  35. TEMPO 3.1: A Body Area Sensor Network Platform for Continuous Movement Assessment. [Citation Graph (, )][DBLP]


  36. At-Speed Delay Characterization for IC Authentication and Trojan Horse Detection. [Citation Graph (, )][DBLP]


  37. IC Activation and User Authentication for Security-Sensitive Systems. [Citation Graph (, )][DBLP]


  38. Performance of Delay-Based Trojan Detection Techniques under Parameter Variations. [Citation Graph (, )][DBLP]


  39. Accelerating Compute-Intensive Applications with GPUs and FPGAs. [Citation Graph (, )][DBLP]


  40. Body Area Sensor Networks: Challenges and Opportunities. [Citation Graph (, )][DBLP]


  41. Application-Specific Product Generics. [Citation Graph (, )][DBLP]


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