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Publications of Author

1. Philip Brisk, Adam Kaplan, Ryan Kastner, Majid Sarrafzadeh
   Instruction generation and regularity extraction for reconfigurable processors. [Citation Graph (0, 0)][DBLP]
   CASES, 2002, pp:262-269 [Conf]
   
2. Philip Brisk, Adam Kaplan, Majid Sarrafzadeh
   Area-efficient instruction set synthesis for reconfigurable system-on-chip designs. [Citation Graph (0, 0)][DBLP]
   DAC, 2004, pp:395-400 [Conf]
   
3. Adam Kaplan, Philip Brisk, Ryan Kastner
   Data communication estimation and reduction for reconfigurable systems. [Citation Graph (0, 0)][DBLP]
   DAC, 2003, pp:616-621 [Conf]
   
4. Ryan Kastner, Wenrui Gong, Xin Hao, Forrest Brewer, Adam Kaplan, Philip Brisk, Majid Sarrafzadeh
   Layout driven data communication optimization for high level synthesis. [Citation Graph (0, 0)][DBLP]
   DATE, 2006, pp:1185-1190 [Conf]
   
5. Philip Brisk, Jamie Macbeth, Ani Nahapetian, Majid Sarrafzadeh
   A dictionary construction technique for code compression systems with echo instructions. [Citation Graph (0, 0)][DBLP]
   LCTES, 2005, pp:105-114 [Conf]
   
6. Roozbeh Jafari, Foad Dabiri, Philip Brisk, Majid Sarrafzadeh
   Adaptive and fault tolerant medical vest for life-critical medical monitoring. [Citation Graph (0, 0)][DBLP]
   SAC, 2005, pp:272-279 [Conf]
   
7. Philip Brisk, Ani Nahapetian, Majid Sarrafzadeh
   Instruction Selection for Compilers that Target Architectures with Echo Instructions. [Citation Graph (0, 0)][DBLP]
   SCOPES, 2004, pp:229-243 [Conf]
   
8. Philip Brisk, Foad Dabiri, Roozbeh Jafari, Majid Sarrafzadeh
   Optimal register sharing for high-level synthesis of SSA form programs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:772-779 [Journal]
   
9. Ajay K. Verma, Philip Brisk, Paolo Ienne
   Rethinking custom ISE identification: a new processor-agnostic method. [Citation Graph (0, 0)][DBLP]
   CASES, 2007, pp:125-134 [Conf]
   
10. Philip Brisk, Ajay K. Verma, Paolo Ienne
    An optimistic and conservative register assignment heuristic for chordal graphs. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:209-217 [Conf]
    
11. Ajay K. Verma, Philip Brisk, Paolo Ienne
    Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:404-409 [Conf]
    
12. Philip Brisk, Ajay K. Verma, Paolo Ienne, Hadi Parandeh-Afshar
    Enhancing FPGA Performance for Arithmetic Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:334-337 [Conf]
    
13. 
    Challenges in Automatic Optimization of Arithmetic Circuits. [Citation Graph (, )][DBLP]
    
    
14. 
    Hybrid LZA: a near optimal implementation of the leading zero anticipator. [Citation Graph (, )][DBLP]
    
    
15. 
    Efficient synthesis of compressor trees on FPGAs. [Citation Graph (, )][DBLP]
    
    
16. 
    Fast, quasi-optimal, and pipelined instruction-set extensions. [Citation Graph (, )][DBLP]
    
    
17. 
    Design space exploration for field programmable compressor trees. [Citation Graph (, )][DBLP]
    
    
18. 
    A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions. [Citation Graph (, )][DBLP]
    
    
19. 
    Speculative DMA for architecturally visible storage in instruction set extensions. [Citation Graph (, )][DBLP]
    
    
20. 
    Thermal-aware data flow analysis. [Citation Graph (, )][DBLP]
    
    
21. 
    Way Stealing: cache-assisted automatic instruction set extensions. [Citation Graph (, )][DBLP]
    
    
22. 
    Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design. [Citation Graph (, )][DBLP]
    
    
23. 
    Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming. [Citation Graph (, )][DBLP]
    
    
24. 
    FPGA Implementation of a Single-Precision Floating-Point Multiply-Accumulator with Single-Cycle Accumulation. [Citation Graph (, )][DBLP]
    
    
25. 
    Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. [Citation Graph (, )][DBLP]
    
    
26. 
    A novel FPGA logic block for improved arithmetic performance. [Citation Graph (, )][DBLP]
    
    
27. 
    3D configuration caching for 2D FPGAs. [Citation Graph (, )][DBLP]
    
    
28. 
    Exploiting fast carry-chains of FPGAs for designing compressor trees. [Citation Graph (, )][DBLP]
    
    
29. 
    Using 3D integration technology to realize multi-context FPGAs. [Citation Graph (, )][DBLP]
    
    
30. 
    MPSoC Design Using Application-Specific Architecturally Visible Communication. [Citation Graph (, )][DBLP]
    
    
31. 
    Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions. [Citation Graph (, )][DBLP]
    
    
32. 
    Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design. [Citation Graph (, )][DBLP]
    
    
33. 
    Memory organization and data layout for instruction set extensions with architecturally visible storage. [Citation Graph (, )][DBLP]
    
    
34. 
    Iterative layering: Optimizing arithmetic circuits by structuring the information flow. [Citation Graph (, )][DBLP]
    
    
35. 
    Interference graphs for procedures in static single information form are interval graphs. [Citation Graph (, )][DBLP]
    
    
36. 
    Introducing control-flow inclusion to support pipelining in custom instruction set extensions. [Citation Graph (, )][DBLP]
    
    
37. 
    Arithmetic optimization for custom instruction set synthesis. [Citation Graph (, )][DBLP]
    
    
38. 
    Scheduling of dataflow models within the Reconfigurable Video Coding framework. [Citation Graph (, )][DBLP]
    
    
39. 
    Architectural support for the orchestration of fine-grained multiprocessing for portable streaming applications. [Citation Graph (, )][DBLP]