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Francisco J. Cazorla: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero
    Architectural support for real-time task scheduling in SMT processors. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:166-176 [Conf]
  2. Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero
    Predictable performance in SMT processors. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:433-443 [Conf]
  3. Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero
    Implicit vs. Explicit Resource Allocation in SMT Processors. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:44-51 [Conf]
  4. Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero
    Feasibility of QoS for SMT. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2004, pp:535-540 [Conf]
  5. Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández
    DCache Warn: An I-Fetch Policy to Increase SMT Efficiency. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  6. Francisco J. Cazorla, Enrique Fernández, Alex Ramírez, Mateo Valero
    Improving Memory Latency Aware Fetch Policies for SMT Processors. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2003, pp:70-85 [Conf]
  7. Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández
    Dynamically Controlled Resource Allocation in SMT Processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:171-182 [Conf]
  8. Adrián Cristal, Oliverio J. Santana, Francisco J. Cazorla, Marco Galluzzi, Tanausú Ramírez, Miquel Pericàs, Mateo Valero
    Kilo-Instruction Processors: Overcoming the Memory Wall. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:3, pp:48-57 [Journal]
  9. Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández
    QoS for High-Performance SMT Processors in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:4, pp:24-31 [Journal]
  10. Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero
    Predictable Performance in SMT Processors: Synergy between the OS and SMTs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:7, pp:785-799 [Journal]
  11. Francisco J. Cazorla, Enrique Fernández, Peter M. W. Knijnenburg, Alex Ramírez, Rizos Sakellariou, Mateo Valero
    On the Problem of Minimizing Workload Execution Time in SMT Processors. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:66-73 [Conf]
  12. Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero
    Online Prediction of Applications Cache Utility. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:169-177 [Conf]

  13. A Flexible Heterogeneous Multi-Core Architecture. [Citation Graph (, )][DBLP]


  14. FAME: FAirly MEasuring Multithreaded Architectures. [Citation Graph (, )][DBLP]


  15. MLP-Aware Dynamic Cache Partitioning. [Citation Graph (, )][DBLP]


  16. ITCA: Inter-task Conflict-Aware CPU Accounting for CMPs. [Citation Graph (, )][DBLP]


  17. Soft Real-Time Scheduling on SMT Processors with Explicit Resource Allocation. [Citation Graph (, )][DBLP]


  18. Load balancing using dynamic cache allocation. [Citation Graph (, )][DBLP]


  19. Using Randomized Caches in Probabilistic Real-Time Systems. [Citation Graph (, )][DBLP]


  20. Architecture Performance Prediction Using Evolutionary Artificial Neural Networks. [Citation Graph (, )][DBLP]


  21. MLP-Aware Dynamic Cache Partitioning. [Citation Graph (, )][DBLP]


  22. MFLUSH: Handling Long-Latency Loads in SMT On-Chip Multiprocessors. [Citation Graph (, )][DBLP]


  23. Balancing HPC applications through smart allocation of resources in MT processors. [Citation Graph (, )][DBLP]


  24. Software-Controlled Priority Characterization of POWER5 Processor. [Citation Graph (, )][DBLP]


  25. A Two-Level Load/Store Queue Based on Execution Locality. [Citation Graph (, )][DBLP]


  26. Hardware support for WCET analysis of hard real-time multicore systems. [Citation Graph (, )][DBLP]


  27. Characterizing the resource-sharing levels in the UltraSPARC T2 processor. [Citation Graph (, )][DBLP]


  28. Thread to strand binding of parallel network applications in massive multi-threaded systems. [Citation Graph (, )][DBLP]


  29. Selection of the Register File Size and the Resource Allocation Policy on SMT Processors. [Citation Graph (, )][DBLP]


  30. Measuring Operating System Overhead on CMT Processors. [Citation Graph (, )][DBLP]


  31. Thread to Core Assignment in SMT On-Chip Multiprocessors. [Citation Graph (, )][DBLP]


  32. A dynamic scheduler for balancing HPC applications. [Citation Graph (, )][DBLP]


  33. Evolutionary system for prediction and optimization of hardware architecture performance. [Citation Graph (, )][DBLP]


  34. Explaining Dynamic Cache Partitioning Speed Ups. [Citation Graph (, )][DBLP]


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