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Oskar Mencer: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ray C. C. Cheung, Dong-U Lee, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung
    Automating custom-precision function evaluation for embedded processors. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:22-31 [Conf]
  2. Dong-U Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk
    MiniBit: bit-width optimization via affine arithmetic. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:837-840 [Conf]
  3. Robert G. Dimond, Oskar Mencer, Wayne Luk
    Automating processor customisation: optimised memory access and resource sharing. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:206-211 [Conf]
  4. Per Haglund, Oskar Mencer, Wayne Luk, Benjamin Tai
    PyHDL: Hardware Scripting with Python. [Citation Graph (0, 0)][DBLP]
    Engineering of Reconfigurable Systems and Algorithms, 2003, pp:288-291 [Conf]
  5. Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung
    Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:79-88 [Conf]
  6. Jian Liang, Russell Tessier, Oskar Mencer
    Floating Point Unit Generation and Evaluation for FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:185-194 [Conf]
  7. Oskar Mencer
    PAM-Blox II: Design and Evaluation of C++ Module Generation for Computing with FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:67-76 [Conf]
  8. Oskar Mencer, Heiko Hübert, Martin Morf, Michael J. Flynn
    StReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:309-312 [Conf]
  9. Oskar Mencer, Martin Morf, Michael J. Flynn
    PAM-Blox: High Performance FPGA Design for Adaptive Computing. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:167-174 [Conf]
  10. Robert G. Dimond, Oskar Mencer, Wayne Luk
    Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:175-184 [Conf]
  11. Evgeny Fiksman, Yitzhak Birk, Oskar Mencer
    ASC-Based Acceleration in an FPGA with a Processor Core Using Software-Only Skills. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:271-272 [Conf]
  12. Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckmann
    FPGAs, GPUs and the PS2 - A Single Programming Methodology. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:313-314 [Conf]
  13. Robert G. Dimond, Oskar Mencer, Wayne Luk
    CUSTARD - A Customisable Threaded FPGA Soft Processor and Tools. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:1-6 [Conf]
  14. Per Haglund, Oskar Mencer, Wayne Luk, Benjamin Tai
    Hardware Design with a Scripting Language. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1040-1043 [Conf]
  15. Dong-U Lee, Oskar Mencer, David J. Pearce, Wayne Luk
    Automating Optimized Table-with-Polynomial Function Evaluation for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:364-373 [Conf]
  16. Oskar Mencer, Nicolas Boullis, Wayne Luk, Henry Styles
    Parameterized Function Evaluation for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:544-554 [Conf]
  17. Oskar Mencer, Zhining Huang, Lorenz Huelsbergen
    HAGAR: Efficient Multi-context Graph Processors. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:915-924 [Conf]
  18. Oskar Mencer, Heiko Hübert, Martin Morf, Michael J. Flynn
    StReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:595-604 [Conf]
  19. M. P. T. Juvonen, José Gabriel F. Coutinho, J. L. Wang, B. L. Lo, Wayne Luk, Oskar Mencer, G. Z. Yang
    Custom Hardware Architectures for Posture Analysis. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:77-84 [Conf]
  20. Oskar Mencer, Marco Platzner
    Dynamic Circuit Generation for Boolean Satisfiability in an Object-Oriented Design Environment. [Citation Graph (0, 0)][DBLP]
    HICSS, 1999, pp:- [Conf]
  21. William H. Mangione-Smith, Brad Hutchins, David L. Andrews, André DeHon, Carl Ebeling, Reiner W. Hartenstein, Oskar Mencer, John Morris, Krishna V. Palem, Viktor K. Prasanna, Henk A. E. Spaanenburg
    Seeking Solutions in Configurable Computing. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1997, v:30, n:12, pp:38-43 [Journal]
  22. Dong-U Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk
    Optimizing Hardware Function Evaluation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:12, pp:1520-1531 [Journal]
  23. Dong-U Lee, Altaf Abdul Gaffar, Ray C. C. Cheung, Oskar Mencer, Wayne Luk, George A. Constantinides
    Accuracy-Guaranteed Bit-Width Optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:1990-2000 [Journal]
  24. Oskar Mencer
    ASC: a stream compiler for computing with FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1603-1617 [Journal]
  25. J. A. Bower, Wayne Luk, Oskar Mencer, Michael J. Flynn, Martin Morf
    Dynamic clock-frequencies for FPGAs. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2006, v:30, n:6, pp:388-397 [Journal]
  26. Kubilay Atasu, Robert G. Dimond, Oskar Mencer, Wayne Luk, Can C. Özturan, Günhan Dündar
    Optimizing instruction-set extensible processors under data bandwidth constraints. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:588-593 [Conf]
  27. Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckmann, Oliver Pell
    Comparing FPGAs to Graphics Accelerators and the Playstation 2 Using a Unified Source Description. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  28. Oskar Mencer, Marco Platzner, Martin Morf, Michael J. Flynn
    Object-oriented domain specific compilers for programming FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:205-210 [Journal]
  29. José Gabriel F. Coutinho, M. P. T. Juvonen, J. L. Wang, B. L. Lo, Wayne Luk, Oskar Mencer, G. Z. Yang
    Designing a Posture Analysis System with Hardware Implementation. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2007, v:47, n:1, pp:33-45 [Journal]

  30. Evaluating Sampling Based Hotspot Detection. [Citation Graph (, )][DBLP]


  31. Fast custom instruction identification by convex subgraph enumeration. [Citation Graph (, )][DBLP]


  32. An Approach to Graph and Netlist Compression. [Citation Graph (, )][DBLP]


  33. Optimizing Logarithmic Arithmetic on FPGAs. [Citation Graph (, )][DBLP]


  34. Power-Aware and Branch-Aware Word-Length Optimization. [Citation Graph (, )][DBLP]


  35. Automatic Accuracy-Guaranteed Bit-Width Optimization for Fixed and Floating-Point Systems. [Citation Graph (, )][DBLP]


  36. Finding Speedup in Parallel Processors. [Citation Graph (, )][DBLP]


  37. Smart Enumeration: A Systematic Approach to Exhaustive Search. [Citation Graph (, )][DBLP]


  38. Reconfigurable design with clock gating. [Citation Graph (, )][DBLP]


  39. A Performance Evaluation of CUBE: One-Dimensional 512 FPGA Cluster. [Citation Graph (, )][DBLP]


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