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Daniel Chillet: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Daniel Menard, Daniel Chillet, François Charot, Olivier Sentieys
    Automatic floating-point to fixed-point conversion for DSP code generation. [Citation Graph (0, 0)][DBLP]
    CASES, 2002, pp:270-276 [Conf]
  2. Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys
    A Compilation Framework for a Dynamically Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1058-1067 [Conf]
  3. Daniel Chillet, Olivier Sentieys, Michel Corazza
    Memory Unit Design for Real Time DSP Applications. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:260-0 [Conf]
  4. Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys
    A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:51-62 [Conf]
  5. Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys
    DART: A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  6. J. O. Dedou, Daniel Chillet, Olivier Sentieys
    Behavioral synthesis of asynchronous systems: a methodology. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:370-373 [Conf]
  7. Sébastien Pillement, Daniel Chillet, Olivier Sentieys
    Behavioral IP Specification and Integration Framework for High-Level Design Reuse. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:388-393 [Conf]
  8. Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Menard, Olivier Sentieys
    Co-Design of Massively Parallel Embedded Processor Architectures. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2005, pp:27-34 [Conf]
  9. François Verdier, Jean-Christophe Prévotet, Amine Benkhelifa, Daniel Chillet, Sébastien Pillement
    Exploring RTOS issues with a high-level model of a reconfigurable SoC platform. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2005, pp:71-78 [Conf]
  10. Daniel Menard, Taofik Saïdi, Daniel Chillet, Olivier Sentieys
    Implantation d'algorithmes spécifiés en virgule flottante dans les DSP virgule fixe. [Citation Graph (0, 0)][DBLP]
    Technique et Science Informatiques, 2003, v:22, n:6, pp:783-803 [Journal]

  11. High-Level Exploration for Dynamic Reconfiguration Management. [Citation Graph (, )][DBLP]


  12. A Neural Network Model for Real-Time Scheduling on Heterogeneous SoC Architectures. [Citation Graph (, )][DBLP]


  13. A Framework for the Exploration of RTOS Dedicated to the Management of Hardware Reconfigurable Resources. [Citation Graph (, )][DBLP]


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