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Srivaths Ravi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Joel Coburn, Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
    SECA: security-enhanced communication architecture. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:78-89 [Conf]
  2. Divya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
    Enhancing security through hardware-assisted run-time validation of program data properties. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:190-195 [Conf]
  3. Divya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
    Architectural support for safe software execution on embedded processors. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:106-111 [Conf]
  4. Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar
    Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:496-501 [Conf]
  5. Li Chen, Srivaths Ravi, Anand Raghunathan, Sujit Dey
    A scalable software-based self-test methodology for programmable processors. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:548-553 [Conf]
  6. Joel Coburn, Srivaths Ravi, Anand Raghunathan
    Power emulation: a new paradigm for power estimation. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:700-705 [Conf]
  7. Pallav Gupta, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Efficient fingerprint-based user authentication for embedded systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:244-247 [Conf]
  8. Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
    Automated energy/performance macromodeling of embedded software. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:99-102 [Conf]
  9. Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
    Hybrid simulation for embedded software energy estimation. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:23-26 [Conf]
  10. Mihalis Psarakis, Dimitris Gizopoulos, Miltiadis Hatzimihail, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi
    Systematic software-based self-test for pipelined processors. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:393-398 [Conf]
  11. Srivaths Ravi, Paul C. Kocher, Ruby B. Lee, Gary McGraw, Anand Raghunathan
    Security as a new dimension in embedded system design. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:753-760 [Conf]
  12. Srivaths Ravi, Anand Raghunathan, Nachiketh R. Potlapally, Murugan Sankaradass
    System design methodologies for a wireless security processing platform. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:777-782 [Conf]
  13. Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Architectures for efficient face authentication in embedded systems. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:1-6 [Conf]
  14. Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:178-183 [Conf]
  15. Davide Bertozzi, Anand Raghunathan, Luca Benini, Srivaths Ravi
    Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10706-10713 [Conf]
  16. Joel Coburn, Srivaths Ravi, Anand Raghunathan
    Hardware Accelerated Power Estimation. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:528-529 [Conf]
  17. Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Energy Estimation for Extensible Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10682-10687 [Conf]
  18. Nachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee
    Satisfiability-based framework for enabling side-channel attacks on cryptographic software. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:18-23 [Conf]
  19. Anand Raghunathan, Srivaths Ravi, Sunil Hattangady, Jean-Jacques Quisquater
    Securing Mobile Appliances: New Challenges for the System Designer. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10176-10183 [Conf]
  20. Indradeep Ghosh, Srivaths Ravi
    On automatic generation of RTL validation test benches using circuit testing techniques. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:289-294 [Conf]
  21. Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    High-level synthesis of distributed logic-memory architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:564-571 [Conf]
  22. Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:46-53 [Conf]
  23. Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    High-level synthesis using computation-unit integrated memories. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:783-790 [Conf]
  24. Vijay Raghunathan, Srivaths Ravi, Anand Raghunathan, Ganesh Lakshminarayana
    Transient Power Management Through High Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:545-552 [Conf]
  25. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
    Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:577-584 [Conf]
  26. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
    A framework for testing core-based systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:385-390 [Conf]
  27. Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Synthesis of custom processors based on extensible platforms. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:641-648 [Conf]
  28. Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    A Scalable Application-Specific Processor Synthesis Methodology. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:283-290 [Conf]
  29. Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Power estimation for cycle-accurate functional descriptions of hardware. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:668-675 [Conf]
  30. Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha
    Test Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based Approach. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:187-193 [Conf]
  31. Srivaths Ravi, Niraj K. Jha, Indradeep Ghosh, Vamsi Boppana
    A Technique for Identifying RTL and Gate-Level Correspondences. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:591-0 [Conf]
  32. Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
    Active Learning Driven Data Acquisition for Sensor Networks. [Citation Graph (0, 0)][DBLP]
    ISCC, 2006, pp:929-934 [Conf]
  33. Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Analyzing the energy consumption of security protocols. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:30-35 [Conf]
  34. Anand Raghunathan, Nachiketh R. Potlapally, Srivaths Ravi
    Securing Wireless Data: System Architecture Challenges. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:195-200 [Conf]
  35. Hiroto Yasuura, Naofumi Takagi, Srivaths Ravi, Michael Torla, Catherine H. Gebotys
    Special Session: Security on SoC. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:192-194 [Conf]
  36. Srivaths Ravi, Niraj K. Jha
    Fast test generation for circuits with RTL and gate-level views. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:1068-1077 [Conf]
  37. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
    : Reducing test application time in high-level test generation. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:829-838 [Conf]
  38. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
    TAO: regular expression based high-level testability analysis and optimization. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:331-340 [Conf]
  39. Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Energy-Optimizing Source Code Transformations for OS-driven Embedded Software. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:261-266 [Conf]
  40. Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar
    Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:65-70 [Conf]
  41. Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha
    Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:299-304 [Conf]
  42. Vijay Raghunathan, Srivaths Ravi, Ganesh Lakshminarayana
    High-Level Synthesis with Variable-Latency Components. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:220-227 [Conf]
  43. Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey
    Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:193-198 [Conf]
  44. Srivaths Ravi, Niraj K. Jha
    Synthesis of System-on-a-chip for Testability. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:149-156 [Conf]
  45. Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
    Embedding Security in Wireless Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:269-270 [Conf]
  46. Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
    Efficient RTL Power Estimation for Large Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:431-439 [Conf]
  47. Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
    Tamper Resistance Mechanisms for Secure, Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:605-0 [Conf]
  48. Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:551-556 [Conf]
  49. Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:473-476 [Conf]
  50. Srivaths Ravi, Stefan Mangard
    Tutorial T1: Designing Secure SoCs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:3- [Conf]
  51. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
    TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:398-406 [Conf]
  52. Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    A hybrid energy-estimation technique for extensible processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:652-664 [Journal]
  53. Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Generation of distributed logic-memory architectures through high-level synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1694-1711 [Journal]
  54. Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Use of Computation-Unit Integrated Memories in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:1969-1989 [Journal]
  55. Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar
    Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2193-2206 [Journal]
  56. Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha
    Satisfiability-based test generation for nonseparable RTL controller-datapath circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:3, pp:544-557 [Journal]
  57. Vijay Raghunathan, Srivaths Ravi, Ganesh Lakshminarayana
    Integrating variable-latency components into high-level synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:10, pp:1105-1117 [Journal]
  58. Srivaths Ravi, Indradeep Ghosh, Vamsi Boppana, Niraj K. Jha
    Fault-diagnosis-based technique for establishing RTL and gate-levelcorrespondences. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:12, pp:1414-1425 [Journal]
  59. Srivaths Ravi, Niraj K. Jha
    Test synthesis of systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1211-1217 [Journal]
  60. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
    TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:8, pp:894-906 [Journal]
  61. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
    Testing of core-based systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:3, pp:426-439 [Journal]
  62. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
    High-level test compaction techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:7, pp:827-841 [Journal]
  63. Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Custom-instruction synthesis for extensible-processor platforms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:2, pp:216-228 [Journal]
  64. Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Application-specific heterogeneous multiprocessor synthesis using extensible processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1589-1602 [Journal]
  65. Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    RTL-Aware Cycle-Accurate Functional Power Estimation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2103-2117 [Journal]
  66. Srivaths Ravi, Anand Raghunathan, Paul C. Kocher, Sunil Hattangady
    Security in embedded systems: Design challenges. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2004, v:3, n:3, pp:461-491 [Journal]
  67. Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    A Study of the Energy Consumption Characteristics of Cryptographic Algorithms and Security Protocols. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Mob. Comput., 2006, v:5, n:2, pp:128-143 [Journal]
  68. Najwa Aaraj, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
    Energy and execution time analysis of a software-based trusted platform module. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1128-1133 [Conf]
  69. Joel Coburn, Srivaths Ravi, Anand Raghunathan
    Hardware Accelerated Power Estimation [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  70. Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    A Scalable Synthesis Methodology for Application-Specific Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:11, pp:1175-1188 [Journal]
  71. Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:12, pp:1295-1308 [Journal]
  72. Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Architectural Support for Run-Time Validation of Program Data Properties. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:546-559 [Journal]
  73. Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:3, pp:296-308 [Journal]
  74. Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha
    Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:605-609 [Journal]
  75. Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar
    Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:6, pp:699-710 [Journal]
  76. Nachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee
    Aiding Side-Channel Attacks on Cryptographic Software With Satisfiability-Based Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:4, pp:465-470 [Journal]
  77. Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
    Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:11, pp:1191-1204 [Journal]
  78. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
    TAO: regular expression-based register-transfer level testability analysis and optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:824-832 [Journal]

  79. Methodology for low power test pattern generation using activity threshold control logic. [Citation Graph (, )][DBLP]


  80. Variability-Tolerant Register-Transfer Level Synthesis. [Citation Graph (, )][DBLP]


  81. A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips. [Citation Graph (, )][DBLP]


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