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Juanjo Noguera: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Juanjo Noguera, Rosa M. Badia
    System-level power-performance trade-offs in task scheduling for dynamically reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:73-83 [Conf]
  2. Juanjo Noguera, Rosa M. Badia
    Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:205-210 [Conf]
  3. Juanjo Noguera, Rosa M. Badia
    Power-performance trade-offs for reconfigurable computing. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:116-121 [Conf]
  4. Juanjo Noguera, Rosa M. Badia
    A HW/SW partitioning algorithm for dynamically reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:729- [Conf]
  5. Juanjo Noguera, Luis Baldez, Narcis Simon, Lluis Abello
    Software-friendly HW/SW co-simulation: an industrial case study. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:100-105 [Conf]
  6. Zexin Pan, Juanjo Noguera, B. Earl Wells
    Improved Microarchitecture Support for Dynamic Task Scheduling on Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    ERSA, 2005, pp:182-188 [Conf]
  7. Juanjo Noguera, Rosa M. Badia, Jordi Domingo-Pascual, Josep Solé-Pareta
    Reconfigurable Computing: An Innovative Solution for Multimedia and Telecommunication Networks Simulation. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:2367-2374 [Conf]
  8. Juanjo Noguera, Rosa M. Badia
    Configuration Prefetching for Non-deterministic Event Driven Multi-context Schedulers. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:842-845 [Conf]
  9. Juanjo Noguera, Rosa M. Badia
    Performance and Energy Analysis of Task-Level Graph Transformation Techniques for Dynamically Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:563-567 [Conf]
  10. Juanjo Noguera, Rosa M. Badia, Jordi Domingo-Pascual, Josep Solé-Pareta
    A HW/SW Codesign-Based Reconfigurable Environment for Telecommunication Network Simulation. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:456-461 [Conf]
  11. Josep Solé-Pareta, Davide Careglio, Salvatore Spadaro, Jaume Masip Torner, Juanjo Noguera, Gabriel Junyent
    Modelling and Performance Evaluation of a National Scale Switchless Based Network. [Citation Graph (0, 0)][DBLP]
    INTERWORKING, 2000, pp:337-347 [Conf]
  12. Juanjo Noguera, Rosa M. Badia
    Run-Time HW/SW Codesign for Discrete Event Systems using Dynamically Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:100-106 [Conf]
  13. Juanjo Noguera, Rosa M. Badia
    Multitasking on reconfigurable architectures: microarchitecture support and dynamic scheduling. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2004, v:3, n:2, pp:385-406 [Journal]
  14. Juanjo Noguera, Rosa M. Badia
    System-level power-performance tradeoffs for reconfigurable computing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:7, pp:730-739 [Journal]
  15. Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil Dutt, Juanjo Noguera
    Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:771-776 [Conf]
  16. Juanjo Noguera, Rosa M. Badia
    HW/SW codesign techniques for dynamically reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:399-415 [Journal]

  17. Generic Software Framework for Adaptive Applications on FPGAs. [Citation Graph (, )][DBLP]


  18. Power Reduction in Network Equipment through Adaptive Partial Reconfiguration. [Citation Graph (, )][DBLP]


  19. Towards Novel Approaches in Design Automation for FPGA Power Optimization. [Citation Graph (, )][DBLP]


  20. Development Framework for Implementing FPGA-Based Cognitive Network Nodes. [Citation Graph (, )][DBLP]


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