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Ann Gordon-Ross:
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- Ann Gordon-Ross, Frank Vahid
Frequent loop detection using efficient non-intrusive on-chip hardware. [Citation Graph (0, 0)][DBLP] CASES, 2003, pp:117-124 [Conf]
- Pablo Viana, Ann Gordon-Ross, Eamonn J. Keogh, Edna Barros, Frank Vahid
Configurable cache subsetting for fast cache tuning. [Citation Graph (0, 0)][DBLP] DAC, 2006, pp:695-700 [Conf]
- Ann Gordon-Ross, Frank Vahid, Nikil Dutt
Automatic Tuning of Two-Level Caches to Embedded Applications. [Citation Graph (0, 0)][DBLP] DATE, 2004, pp:208-213 [Conf]
- Ann Gordon-Ross, Frank Vahid, Nikil Dutt
A first look at the interplay of code reordering and configurable caches. [Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2005, pp:416-421 [Conf]
- Ann Gordon-Ross, Frank Vahid
Dynamic Loop Caching Meets Preloaded Loop Caching - A Hybrid Approach. [Citation Graph (0, 0)][DBLP] ICCD, 2002, pp:446-449 [Conf]
- Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt
Fast configurable-cache tuning with a unified second-level cache. [Citation Graph (0, 0)][DBLP] ISLPED, 2005, pp:323-326 [Conf]
- Frank Vahid, Ann Gordon-Ross
A self-optimizing embedded microprocessor using a loop table for low power. [Citation Graph (0, 0)][DBLP] ISLPED, 2001, pp:219-224 [Conf]
- Ann Gordon-Ross, Susan Cotterell, Frank Vahid
Exploiting Fixed Programs in Embedded Systems: A Loop Cache Example. [Citation Graph (0, 0)][DBLP] Computer Architecture Letters, 2002, v:1, n:, pp:- [Journal]
- Ann Gordon-Ross, Frank Vahid
Frequent Loop Detection Using Efficient Nonintrusive On-Chip Hardware. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 2005, v:54, n:10, pp:1203-1215 [Journal]
- Ann Gordon-Ross, Susan Cotterell, Frank Vahid
Tiny instruction caches for low power embedded systems. [Citation Graph (0, 0)][DBLP] ACM Trans. Embedded Comput. Syst., 2003, v:2, n:4, pp:449-481 [Journal]
- Ann Gordon-Ross, Frank Vahid
A Self-Tuning Configurable Cache. [Citation Graph (0, 0)][DBLP] DAC, 2007, pp:234-237 [Conf]
- Ann Gordon-Ross, Pablo Viana, Frank Vahid, Walid A. Najjar, Edna Barros
A one-shot configurable-cache tuner for improved energy and performance. [Citation Graph (0, 0)][DBLP] DATE, 2007, pp:755-760 [Conf]
An MDP-based application oriented optimal policy for wireless sensor networks. [Citation Graph (, )][DBLP]
Bitstream relocation with local clock domains for partially reconfigurable FPGAs. [Citation Graph (, )][DBLP]
SCORES: A scalable and parametric streams-based communication architecture for modular reconfigurable systems. [Citation Graph (, )][DBLP]
VAPRES: A Virtual Architecture for Partially Reconfigurable Embedded Systems. [Citation Graph (, )][DBLP]
Design Framework for Partial Run-Time FPGA Reconfiguration. [Citation Graph (, )][DBLP]
Exploiting Partially Reconfigurable FPGAs for Situation-Based Reconfiguration in Wireless Sensor Networks. [Citation Graph (, )][DBLP]
Macs: A Minimal Adaptive routing circuit-switched architecture for scalable and parametric NoCs. [Citation Graph (, )][DBLP]
A table-based method for single-pass cache optimization. [Citation Graph (, )][DBLP]
Phase-based cache reconfiguration for a highly-configurable two-level cache hierarchy. [Citation Graph (, )][DBLP]
Lightweight runtime control flow analysis for adaptive loop caching. [Citation Graph (, )][DBLP]
A resource efficient content inspection system for next generation Smart NICs. [Citation Graph (, )][DBLP]
Smart-NICs: Power Proxying for Reduced Power Consumption in Network Edge Devices. [Citation Graph (, )][DBLP]
Real-time performance analysis of Adaptive Link Rate. [Citation Graph (, )][DBLP]
Transaction-Level Modeling for Sensor Networks Using SystemC. [Citation Graph (, )][DBLP]
SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems. [Citation Graph (, )][DBLP]
SIP-Based IMS Registration Analysis for WiMax-3G Interworking Architectures. [Citation Graph (, )][DBLP]
Runtime Temporal Partitioning Assembly to Reduce FPGA Reconfiguration Time. [Citation Graph (, )][DBLP]
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