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Alex K. Jones :
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Alex K. Jones , Debabrata Bagchi , Satrajit Pal , Xiaoyong Tang , Alok N. Choudhary , Prithviraj Banerjee PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations. [Citation Graph (0, 0)][DBLP ] CASES, 2002, pp:188-197 [Conf ] Alex K. Jones , Raymond R. Hoare , Swapna R. Dontharaju , Shen Chih Tung , Ralph Sprang , Joshua Fazekas , James T. Cain , Marlin H. Mickle An automated, reconfigurable, low-power RFID tag. [Citation Graph (0, 0)][DBLP ] DAC, 2006, pp:131-136 [Conf ] Prithviraj Banerjee , Nagaraj Shenoy , Alok N. Choudhary , Scott Hauck , C. Bachmann , Malay Haldar , Pramod G. Joisha , Alex K. Jones , Abhay Kanhere , Anshuman Nayak , S. Periyacheri , M. Walkden , David Zaretsky A MATLAB Compiler for Distributed, Heterogeneous, Reconfigurable Computing Systems. [Citation Graph (0, 0)][DBLP ] FCCM, 2000, pp:39-48 [Conf ] Alex K. Jones , Prithviraj Banerjee An Automated and Power-Aware Framework for Utilization of IP Cores in Hardware Generated from C Descriptions Targeting FPGAs. [Citation Graph (0, 0)][DBLP ] FCCM, 2003, pp:284-285 [Conf ] Joshua M. Lucas , Raymond Hoare , Alex K. Jones Optimizing Technology Mapping for FPGAs Using CAMs. [Citation Graph (0, 0)][DBLP ] FCCM, 2005, pp:293-294 [Conf ] Gayatri Mehta , Raymond R. Hoare , Justin Stander , Alex K. Jones A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture. [Citation Graph (0, 0)][DBLP ] FCCM, 2006, pp:309-310 [Conf ] Alex K. Jones , Raymond R. Hoare , Swapna R. Dontharaju , Shen Chih Tung , Ralph Sprang , Joshua Fazekas , James T. Cain , Marlin H. Mickle A Field Programmable RFID Tag and Associated Design Flow. [Citation Graph (0, 0)][DBLP ] FCCM, 2006, pp:165-174 [Conf ] Raymond R. Hoare , Ivan S. Kourtev , Alex K. Jones Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM). [Citation Graph (0, 0)][DBLP ] FCCM, 2006, pp:299-300 [Conf ] Alex K. Jones , Prithviraj Banerjee An automated and power-aware framework for utilization of IP cores in hardware generated from C descriptions targeting FPGAs. [Citation Graph (0, 0)][DBLP ] FPGA, 2003, pp:244- [Conf ] Alex K. Jones , Raymond Hoare , Dara Kusic , Joshua Fazekas , John Foster An FPGA-based VLIW processor with custom hardware execution. [Citation Graph (0, 0)][DBLP ] FPGA, 2005, pp:107-117 [Conf ] Zhu Ding , Raymond R. Hoare , Alex K. Jones , Dan Li , Shou-Kuo Shao , Shen-Chien Tung , Jiang Zheng , Rami G. Melhem Switch Design to Enable Predictive Multiplexed Switching in Multiprocessor Networks. [Citation Graph (0, 0)][DBLP ] IPDPS, 2005, pp:- [Conf ] Dara Kusic , Raymond Hoare , Alex K. Jones , Joshua Fazekas , John Foster Extracting Speedup From C-Code With Poor Instruction-Level Parallelism. [Citation Graph (0, 0)][DBLP ] IPDPS, 2005, pp:- [Conf ] Gayatri Mehta , Raymond R. Hoare , Justin Stander , Alex K. Jones Design space exploration for low-power reconfigurable fabrics. [Citation Graph (0, 0)][DBLP ] IPDPS, 2006, pp:- [Conf ] Shuyi Shao , Alex K. Jones , Rami G. Melhem A compiler-based communication analysis approach for multiprocessor systems. [Citation Graph (0, 0)][DBLP ] IPDPS, 2006, pp:- [Conf ] Rajarshi Mukherjee , Alex K. Jones , Prithviraj Banerjee Handling Data Streams while Compiling C Programs onto Hardware. [Citation Graph (0, 0)][DBLP ] ISVLSI, 2004, pp:271-272 [Conf ] Kevin J. Barker , Alan F. Benner , Raymond R. Hoare , Adolfy Hoisie , Alex K. Jones , Darren J. Kerbyson , Dan Li , Rami G. Melhem , Ramakrishnan Rajamony , Eugen Schenfeld , Shuyi Shao , Craig B. Stunkel , Peter Walker On the Feasibility of Optical Circuit Switching for High Performance Computing Systems. [Citation Graph (0, 0)][DBLP ] SC, 2005, pp:16- [Conf ] Zhu Ding , Raymond R. Hoare , Alex K. Jones , Rami G. Melhem Interconnect routing and scheduling - Level-wise scheduling algorithm for fat tree interconnection networks. [Citation Graph (0, 0)][DBLP ] SC, 2006, pp:96- [Conf ] Raymond R. Hoare , Zhu Ding , Alex K. Jones Interconnect routing and scheduling - A near-optimal real-time hardware scheduler for large cardinality crossbar switches. [Citation Graph (0, 0)][DBLP ] SC, 2006, pp:94- [Conf ] Xiaoyong Tang , Tianyi Jiang , Alex K. Jones , Prithviraj Banerjee Behavioral Synthesis of Data-Dominated Circuits for Minimal Energy Implementation. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2005, pp:267-273 [Conf ] Raymond R. Hoare , Zhu Ding , Shen Chih Tung , Rami G. Melhem , Alex K. Jones A framework for the design, synthesis and cycle-accurate simulation of multiprocessor networks. [Citation Graph (0, 0)][DBLP ] J. Parallel Distrib. Comput., 2005, v:65, n:10, pp:1237-1252 [Journal ] Alex K. Jones , Raymond Hoare , Dara Kusic , Gayatri Mehta , Joshua Fazekas , John Foster Reducing power while increasing performance with supercisc. [Citation Graph (0, 0)][DBLP ] ACM Trans. Embedded Comput. Syst., 2006, v:5, n:3, pp:658-686 [Journal ] Joshua M. Lucas , Raymond Hoare , Ivan S. Kourtev , Alex K. Jones Technology mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM). [Citation Graph (0, 0)][DBLP ] Microprocessors and Microsystems, 2006, v:30, n:7, pp:445-456 [Journal ] Alex K. Jones , Raymond Hoare , Swapna R. Dontharaju , Shen Chih Tung , Ralph Sprang , Joshua Fazekas , James T. Cain , Marlin H. Mickle An automated, FPGA-based reconfigurable, low-power RFID tag. [Citation Graph (0, 0)][DBLP ] Microprocessors and Microsystems, 2007, v:31, n:2, pp:116-134 [Journal ] Gayatri Mehta , Justin Stander , Mustafa Baz , Brady Hunsaker , Alex K. Jones Interconnect Customization for a Coarse-grained Reconfigurable Fabric. [Citation Graph (0, 0)][DBLP ] IPDPS, 2007, pp:1-8 [Conf ] Alex K. Jones , Raymond R. Hoare , Joseph St. Onge , Joshua M. Lucas , Shuyi Shao , Rami G. Melhem Linking Compilation and Visualization for Massively Parallel Programs. [Citation Graph (0, 0)][DBLP ] IPDPS, 2007, pp:1-8 [Conf ] Colin J. Ihrig , Justin Stander , Alex K. Jones Pipelining Tradeoffs of Massively Parallel SuperCISC Hardware Functions. [Citation Graph (0, 0)][DBLP ] IPDPS, 2007, pp:1-8 [Conf ] Ying Yu , Raymond R. Hoare , Alex K. Jones , Ralph Sprang A hybrid encoding scheme for efficient single-cycle range matching in content addressable memory. [Citation Graph (0, 0)][DBLP ] ISCAS, 2006, pp:- [Conf ] Xiaoyong Tang , Tianyi Jiang , Alex K. Jones , Prithviraj Banerjee High-Level Synthesis for Low Power Hardware Implementation of Unscheduled Data-Dominated Circuits. [Citation Graph (0, 0)][DBLP ] J. Low Power Electronics, 2005, v:1, n:3, pp:259-272 [Journal ] Gayatri Mehta , Justin Stander , Joshua M. Lucas , Raymond R. Hoare , Brady Hunsaker , Alex K. Jones A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture. [Citation Graph (0, 0)][DBLP ] J. Low Power Electronics, 2006, v:2, n:2, pp:148-164 [Journal ] Automated modeling and emulation of interconnect designs for many-core chip multiprocessors. [Citation Graph (, )][DBLP ] A low-power CMOS thyristor based delay element with programmability extensions. [Citation Graph (, )][DBLP ] Reducing energy by exploring heterogeneity in a coarse-grain fabric. [Citation Graph (, )][DBLP ] Symbolic expression analysis for compiled communication. [Citation Graph (, )][DBLP ] A CAM-based intrusion detection system for single-packet attack detection. [Citation Graph (, )][DBLP ] Physical layer design automation for RFID systems. [Citation Graph (, )][DBLP ] Non-uniform fat-meshes for chip multiprocessors. [Citation Graph (, )][DBLP ] Search in 0.019secs, Finished in 0.021secs