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Publications of Author

1. Alex K. Jones, Debabrata Bagchi, Satrajit Pal, Xiaoyong Tang, Alok N. Choudhary, Prithviraj Banerjee
   PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations. [Citation Graph (0, 0)][DBLP]
   CASES, 2002, pp:188-197 [Conf]
   
2. Prithviraj Banerjee, Debabrata Bagchi, Malay Haldar, Anshuman Nayak, Victor Kim, R. Uribe
   Automatic Conversion of Floating Point MATLAB Programs into Fixed Point FPGA Based Hardware Design. [Citation Graph (0, 0)][DBLP]
   FCCM, 2003, pp:263-264 [Conf]
   
3. Prithviraj Banerjee, Vikram Saxena, J. R. Uribe, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, R. Anderson
   Making area-performance tradeoffs at the high level using the AccelFPGA compiler for FPGAs. [Citation Graph (0, 0)][DBLP]
   FPGA, 2003, pp:237- [Conf]
   
4. Prithviraj Banerjee, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi
   A Behavioral Synthesis Tool for Exploiting Fine Grain Parallelism in FPGAs. [Citation Graph (0, 0)][DBLP]
   IWDC, 2002, pp:246-256 [Conf]
   
5. Debabrata Bagchi, Dipanwita Roy Chowdhury, Joy Mukherjee, Santanu Chattopadhyay
   A Novel Strategy to Test Core Based Designs. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2001, pp:122-127 [Conf]
   
6. Prithviraj Banerjee, Malay Haldar, Anshuman Nayak, Victor Kim, Vikram Saxena, Steven Parkes, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, David Zaretsky, R. Anderson, J. R. Uribe
   Overview of a compiler for synthesizing MATLAB programs onto FPGAs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2004, v:12, n:3, pp:312-324 [Journal]
   
7. 
   Leveraging UPF-extracted assertions for modeling and formal verification of architectural power intent. [Citation Graph (, )][DBLP]