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Xiaoyong Tang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Alex K. Jones, Debabrata Bagchi, Satrajit Pal, Xiaoyong Tang, Alok N. Choudhary, Prithviraj Banerjee
    PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations. [Citation Graph (0, 0)][DBLP]
    CASES, 2002, pp:188-197 [Conf]
  2. Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee
    Automatic translation of software binaries onto FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:389-394 [Conf]
  3. Xiaoyong Tang, Hai Zhou, Prithviraj Banerjee
    Leakage power optimization with dual-Vth library in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:202-207 [Conf]
  4. David Zaretsky, Gaurav Mittal, Xiaoyong Tang, Prithviraj Banerjee
    Overview of the FREEDOM Compiler for Mapping DSP Software to FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:37-46 [Conf]
  5. Tianyi Jiang, Xiaoyong Tang, Prithviraj Banerjee
    High level area, delay and power estimation for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:249- [Conf]
  6. Tianyi Jiang, Xiaoyong Tang, Prithviraj Banerjee
    Macro-models for high level area and power estimation on FPGAs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:162-165 [Conf]
  7. David Zaretsky, Gaurav Mittal, Xiaoyong Tang, Prithviraj Banerjee
    Evaluation of scheduling and allocation algorithms while mapping assembly code onto FPGAs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:397-400 [Conf]
  8. Xiaoyong Tang, Kenli Li, Degui Xiao, Jing Yang, Min Liu, Yunchuan Qin
    A Dynamic Communication Contention Awareness List Scheduling Algorithm for Arbitrary Heterogeneous System. [Citation Graph (0, 0)][DBLP]
    OTM Conferences (2), 2006, pp:1315-1324 [Conf]
  9. Chunling Zhu, Xiaoyong Tang, Kenli Li, Xiao Han, Xilu Zhu, Xuesheng Qi
    Integrating Trust into Grid Economic Model Scheduling Algorithm. [Citation Graph (0, 0)][DBLP]
    OTM Conferences (2), 2006, pp:1263-1272 [Conf]
  10. Xiaoyong Tang, Tianyi Jiang, Alex K. Jones, Prithviraj Banerjee
    Behavioral Synthesis of Data-Dominated Circuits for Minimal Energy Implementation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:267-273 [Conf]
  11. Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee
    An Overview of a Compiler for Mapping Software Binaries to Hardware. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:11, pp:1177-1190 [Journal]
  12. Xiaoyong Tang, Tianyi Jiang, Alex K. Jones, Prithviraj Banerjee
    High-Level Synthesis for Low Power Hardware Implementation of Unscheduled Data-Dominated Circuits. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:3, pp:259-272 [Journal]

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