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Zhigang Hu:
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Publications of Author
- Stefanos Kaxiras, Girija J. Narlikar, Alan D. Berenbaum, Zhigang Hu
Comparing power consumption of an SMT and a CMP DSP for mobile phone workloads. [Citation Graph (0, 0)][DBLP] CASES, 2001, pp:211-220 [Conf]
- Zhigang Hu, Margaret Martonosi, Stefanos Kaxiras
TCP: Tag Correlating Prefetchers. [Citation Graph (0, 0)][DBLP] HPCA, 2003, pp:317-326 [Conf]
- Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Rick Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler
Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors. [Citation Graph (0, 0)][DBLP] HPCA, 2005, pp:238-242 [Conf]
- Russ Joseph, Zhigang Hu, Margaret Martonosi
Wavelet Analysis for Microprocessor Design: Experiences with Wavelet-Based dI/dt Characterization. [Citation Graph (0, 0)][DBLP] HPCA, 2004, pp:36-47 [Conf]
- Yingmin Li, David Brooks, Zhigang Hu, Kevin Skadron
Performance, Energy, and Thermal Considerations for SMT and CMP Architectures. [Citation Graph (0, 0)][DBLP] HPCA, 2005, pp:71-82 [Conf]
- Zhigang Hu, Philo Juang, Kevin Skadron, Douglas W. Clark, Margaret Martonosi
Applying Decay Strategies to Branch Predictors for Leakage Energy Savings. [Citation Graph (0, 0)][DBLP] ICCD, 2002, pp:442-445 [Conf]
- Zhigang Hu, Margaret Martonosi, Stefanos Kaxiras
Timekeeping in the Memory System: Predicting and Optimizing Memory Behavior. [Citation Graph (0, 0)][DBLP] ISCA, 2002, pp:209-220 [Conf]
- Stefanos Kaxiras, Zhigang Hu, Margaret Martonosi
Cache decay: exploiting generational behavior to reduce cache leakage power. [Citation Graph (0, 0)][DBLP] ISCA, 2001, pp:240-251 [Conf]
- Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor V. Zyuban, Hans M. Jacobson, Pradip Bose
Microarchitectural techniques for power gating of execution units. [Citation Graph (0, 0)][DBLP] ISLPED, 2004, pp:32-37 [Conf]
- Zhigang Hu, Philo Juang, Phil Diodato, Stefanos Kaxiras, Kevin Skadron, Margaret Martonosi, Douglas W. Clark
Managing leakage for transient data: decay and quasi-static 4T memory cells. [Citation Graph (0, 0)][DBLP] ISLPED, 2002, pp:52-55 [Conf]
- Yingmin Li, David Brooks, Zhigang Hu, Kevin Skadron, Pradip Bose
Understanding the energy efficiency of simultaneous multithreading. [Citation Graph (0, 0)][DBLP] ISLPED, 2004, pp:44-49 [Conf]
- Yingmin Li, Mark Hempstead, Patrick Mauro, David Brooks, Zhigang Hu, Kevin Skadron
Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices. [Citation Graph (0, 0)][DBLP] ISLPED, 2005, pp:173-178 [Conf]
- Russ Joseph, Margaret Martonosi, Zhigang Hu
Spectral analysis for characterizing program power and performance. [Citation Graph (0, 0)][DBLP] ISPASS, 2004, pp:151-160 [Conf]
- Stefanos Kaxiras, Zhigang Hu, Girija J. Narlikar, Rae McLellan
Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power. [Citation Graph (0, 0)][DBLP] PACS, 2000, pp:82-96 [Conf]
- Rong Hu, Zhigang Hu, Hao Ma
A Reliable Routing Algorithm Based on Fuzzy Applicability of F sets in MANET. [Citation Graph (0, 0)][DBLP] PRDC, 2005, pp:245-249 [Conf]
- Hendrik F. Hamann, Alan J. Weger, James Lacey, Zhigang Hu, Pradip Bose, Erwin Cohen, Jamil A. Wakil
Temperature-limited microprocessors: Measurements and design implications. [Citation Graph (0, 0)][DBLP] VLSI Design, 2007, pp:427-432 [Conf]
- Philo Juang, Phil Diodato, Stefanos Kaxiras, Kevin Skadron, Zhigang Hu, Margaret Martonosi, Douglas W. Clark
Implementing Decay Techniques using 4T Quasi-Static Memory Cells. [Citation Graph (0, 0)][DBLP] Computer Architecture Letters, 2002, v:1, n:, pp:- [Journal]
- Philo Juang, Kevin Skadron, Margaret Martonosi, Zhigang Hu, Douglas W. Clark, Phil Diodato, Stefanos Kaxiras
Implementing branch-predictor decay using quasi-static memory cells. [Citation Graph (0, 0)][DBLP] TACO, 2004, v:1, n:2, pp:180-219 [Journal]
- Zhigang Hu, Stefanos Kaxiras, Margaret Martonosi
Let caches decay: reducing leakage energy via exploitation of cache generational behavior. [Citation Graph (0, 0)][DBLP] ACM Trans. Comput. Syst., 2002, v:20, n:2, pp:161-190 [Journal]
- Jeonghee Shin, Victor V. Zyuban, Zhigang Hu, Jude A. Rivers, Pradip Bose
A Framework for Architecture-Level Lifetime Reliability Modeling. [Citation Graph (0, 0)][DBLP] DSN, 2007, pp:534-543 [Conf]
A Novel Trust Model Based on Bayesian Network for Service-Oriented Grid. [Citation Graph (, )][DBLP]
Exploring power management in multi-core systems. [Citation Graph (, )][DBLP]
CMP design space exploration subject to physical constraints. [Citation Graph (, )][DBLP]
Deadline-Guarantee-Enhanced Co-Allocation for Parameter Sweep Application in Grid. [Citation Graph (, )][DBLP]
A Novel QoS-Based Co-Allocation Model in Computational Grid. [Citation Graph (, )][DBLP]
Bayesian Network based QoS Trustworthiness Evaluation Method in Service Oriented Grid. [Citation Graph (, )][DBLP]
A Novel Statistic-based Relaxed Grid Resource Reservation Strategy. [Citation Graph (, )][DBLP]
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