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Subramanian Rajagopalan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Subramanian Rajagopalan, Manish Vachharajani, Sharad Malik
    Handling irregular ILP within conventional VLIW schedulers using artificial resource constraints. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:157-164 [Conf]
  2. Guilherme Ottoni, Sandro Rigo, Guido Araujo, Subramanian Rajagopalan, Sharad Malik
    Optimal Live Range Merge for Address Register Allocation in Embedded Programs. [Citation Graph (0, 0)][DBLP]
    CC, 2001, pp:274-288 [Conf]
  3. Wei Qin, Subramanian Rajagopalan, Manish Vachharajani, Hangsheng Wang, Xinping Zhu, David I. August, Kurt Keutzer, Sharad Malik, Li-Shiuan Peh
    Design Tools for Application Specific Embedded Processors. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2002, pp:319-333 [Conf]
  4. Wei Qin, Subramanian Rajagopalan, Sharad Malik
    A formal concurrency model based architecture description language for synthesis of software development tools. [Citation Graph (0, 0)][DBLP]
    LCTES, 2004, pp:47-56 [Conf]
  5. Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou
    Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:875-880 [Conf]
  6. Subramanian Rajagopalan, Shabbir H. Batterywala
    A 3-dimensional FEM Based Resistance Extraction. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:565-570 [Conf]
  7. Subramanian Rajagopalan, Sreeranga P. Rajan, Sharad Malik, Sandro Rigo, Guido Araujo, Koichiro Takayama
    A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:11, pp:1319-1328 [Journal]

  8. On Efficient and Robust Constraint Generation for Practical Layout Legalization. [Citation Graph (, )][DBLP]

  9. Cell Swapping Based Migration Methodology for Analog and Custom Layouts. [Citation Graph (, )][DBLP]

  10. Efficient Analog/RF Layout Closure with Compaction Based Legalization. [Citation Graph (, )][DBLP]

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