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Indira Nair: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Valentina Salapura, Christos J. Georgiou, Indira Nair
    An efficient system-on-a-chip design methodology for networking applications. [Citation Graph (0, 0)][DBLP]
    CASES, 2004, pp:212-219 [Conf]
  2. Reinaldo A. Bergamaschi, Youngsoo Shin, Nagu R. Dhanwada, Subhrajit Bhattacharya, William E. Dougherty, Indira Nair, John A. Darringer, Sarala Paliwal
    SEAS: a system for early analysis of SoCs. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:150-155 [Conf]
  3. Ashok K. Chandra, Vijay S. Iyengar, R. V. Jawalekar, Michael P. Mullen, Indira Nair, Barry K. Rosen
    Architectural Verification of Processors Using Symbolic Instruction Graphs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:454-459 [Conf]
  4. Zeev Barzilai, J. Lawrence Carter, Vijay S. Iyengar, Indira Nair, Barry K. Rosen, Joe D. Rutledge, Gabriel M. Silberman
    Efficient Fault Simulation of CMOS Circuits with Accurate Models. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:520-529 [Conf]
  5. Sandip Kundu, Leendert M. Huisman, Indira Nair, Vijay S. Iyengar, Lakshmi N. Reddy
    A Small Test Generator for Large Designs. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:30-40 [Conf]
  6. John A. Darringer, Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Daniel Brand, Andreas Herkersdorf, Joseph K. Morrell, Indira Nair, Patricia Sagmeister, Youngsoo Shin
    Early analysis tools for system-on-a-chip design. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2002, v:46, n:6, pp:691-708 [Journal]
  7. Ashok K. Chandra, Vijay S. Iyengar, D. Jameson, R. V. Jawalekar, Indira Nair, Barry K. Rosen, Michael P. Mullen, J. Yoon, R. Armoni, Daniel Geist, Yaron Wolfsthal
    AVPGEN-A test generator for architecture verification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:2, pp:188-200 [Journal]
  8. Reinaldo A. Bergamaschi, Salil Raje, Indira Nair, Louise Trevillyan
    Control-flow versus data-flow-based scheduling: combining both approaches in an adaptive scheduling system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:1, pp:82-100 [Journal]

  9. Exploring power management in multi-core systems. [Citation Graph (, )][DBLP]

  10. Performance modeling for early analysis of multi-core systems. [Citation Graph (, )][DBLP]

  11. Power-efficient, reliable microprocessor architectures: modeling and design methods. [Citation Graph (, )][DBLP]

  12. Power Management and Its Impact on Power Supply Noise. [Citation Graph (, )][DBLP]

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