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Greg Stitt: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Greg Stitt, Frank Vahid, Tony Givargis, Roman L. Lysecky
    A first-step towards an architecture tuning methodology for low power. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:187-192 [Conf]
  2. Brian Grattan, Greg Stitt, Frank Vahid
    Codesign-extended applications. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:1-6 [Conf]
  3. Greg Stitt, Frank Vahid, Gordon McGregor, Brian Einloth
    Hardware/software partitioning of software binaries: a case study of H.264 decode. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:285-290 [Conf]
  4. Greg Stitt, Roman L. Lysecky, Frank Vahid
    Dynamic hardware/software partitioning: a first approach. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:250-255 [Conf]
  5. Greg Stitt, Frank Vahid
    A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:396-397 [Conf]
  6. Greg Stitt, Brian Grattan, Jason R. Villarreal, Frank Vahid
    Using On-Chip Configurable Logic to Reduce Embedded System Software Energy. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:143-151 [Conf]
  7. Greg Stitt, Zhi Guo, Walid A. Najjar, Frank Vahid
    Techniques for synthesizing binaries to an advanced register/memory structure. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:118-124 [Conf]
  8. Greg Stitt, Frank Vahid
    Hardware/software partitioning of software binaries. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:164-170 [Conf]
  9. Greg Stitt, Frank Vahid, Walid A. Najjar
    A code refinement methodology for performance-improved synthesis from C. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:716-723 [Conf]
  10. Dinesh C. Suresh, Walid A. Najjar, Frank Vahid, Jason R. Villarreal, Greg Stitt
    Profiling tools for hardware/software partitioning of embedded applications. [Citation Graph (0, 0)][DBLP]
    LCTES, 2003, pp:189-198 [Conf]
  11. Greg Stitt, Frank Vahid
    Energy Advantages of Microprocessor Platforms with On-Chip Configurable Logic. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:6, pp:36-43 [Journal]
  12. Frank Vahid, Rilesh Patel, Greg Stitt
    Propagating constants past software to hardware peripherals in fixed-application embedded systems. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2001, v:29, n:5, pp:25-30 [Journal]
  13. Greg Stitt, Frank Vahid, Shawn Nematbakhsh
    Energy savings and speedups from partitioning critical software loops to hardware in embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2004, v:3, n:1, pp:218-232 [Journal]
  14. Roman L. Lysecky, Greg Stitt, Frank Vahid
    Warp Processors. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:3, pp:659-681 [Journal]
  15. Greg Stitt, Frank Vahid
    A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  16. Greg Stitt, Frank Vahid
    Binary synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:3, pp:- [Journal]
  17. Frank Vahid, Roman L. Lysecky, Chuanjun Zhang, Greg Stitt
    Highly configurable platforms for embedded computing systems. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2003, v:34, n:11, pp:1025-1029 [Journal]

  18. Thread warping: a framework for dynamic synthesis of thread accelerators. [Citation Graph (, )][DBLP]

  19. Traversal caches: a first step towards FPGA acceleration of pointer-based data structures. [Citation Graph (, )][DBLP]

  20. C is for circuits: capturing FPGA circuits as sequential code for portability. [Citation Graph (, )][DBLP]

  21. Recursion flattening. [Citation Graph (, )][DBLP]

  22. Hardware/software partitioning with multi-version implementation exploration. [Citation Graph (, )][DBLP]

  23. Elastic computing: a framework for transparent, portable, and adaptive multi-core heterogeneous computing. [Citation Graph (, )][DBLP]

  24. A framework for core-level modeling and design of reconfigurable computing algorithms. [Citation Graph (, )][DBLP]

  25. Bridging parallel and reconfigurable computing with multilevel PGAS and SHMEM+. [Citation Graph (, )][DBLP]

  26. SCF: a device- and language-independent task coordination framework for reconfigurable, heterogeneous systems. [Citation Graph (, )][DBLP]

  27. A Traversal Cache Framework for FPGA Acceleration of Pointer Data Structures: A Case Study on Barnes-Hut N-body Simulation. [Citation Graph (, )][DBLP]

  28. Warp Processing: Dynamic Translation of Binaries to FPGA Circuits. [Citation Graph (, )][DBLP]

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