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Roman L. Lysecky: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Greg Stitt, Frank Vahid, Tony Givargis, Roman L. Lysecky
    A first-step towards an architecture tuning methodology for low power. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:187-192 [Conf]
  2. Roman L. Lysecky, Frank Vahid
    A codesigned on-chip logic minimizer. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:109-113 [Conf]
  3. Roman L. Lysecky, Susan Cotterell, Frank Vahid
    A fast on-chip profiler memory. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:28-33 [Conf]
  4. Roman L. Lysecky, Frank Vahid
    On-chip logic minimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:334-337 [Conf]
  5. Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
    Dynamic FPGA routing for just-in-time FPGA compilation. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:954-959 [Conf]
  6. Greg Stitt, Roman L. Lysecky, Frank Vahid
    Dynamic hardware/software partitioning: a first approach. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:250-255 [Conf]
  7. Roman L. Lysecky, Frank Vahid
    A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:480-485 [Conf]
  8. Roman L. Lysecky, Frank Vahid
    A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:18-23 [Conf]
  9. Roman L. Lysecky, Frank Vahid, Tony Givargis
    Techniques for Reducing Read Latency of Core Bus Wrappers. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:84-91 [Conf]
  10. Chuanjun Zhang, Frank Vahid, Roman L. Lysecky
    A Self-Tuning Cache Architecture for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:142-147 [Conf]
  11. Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
    A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:57-62 [Conf]
  12. Roman L. Lysecky, Kris Miller, Frank Vahid, Kees A. Vissers
    Firm-core Virtual FPGA for Just-in-Time FPGA Compilation (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:271- [Conf]
  13. David Sheldon, Rakesh Kumar, Roman L. Lysecky, Frank Vahid, Dean M. Tullsen
    Application-specific customization of parameterized FPGA soft-core processors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:261-268 [Conf]
  14. David Sheldon, Rakesh Kumar, Frank Vahid, Dean M. Tullsen, Roman L. Lysecky
    Conjoining soft-core FPGA processors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:694-701 [Conf]
  15. Roman L. Lysecky, Frank Vahid, Tony Givargis
    Experiments with the Peripheral Virtual Component Interface. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:221-224 [Conf]
  16. Roman L. Lysecky, Frank Vahid, Rilesh Patel, Tony Givargis
    Pre-Fetching for Improved Core Interfacing. [Citation Graph (0, 0)][DBLP]
    ISSS, 1999, pp:51-55 [Conf]
  17. Chuanjun Zhang, Frank Vahid, Roman L. Lysecky
    A self-tuning cache architecture for embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2004, v:3, n:2, pp:407-425 [Journal]
  18. Roman L. Lysecky, Frank Vahid
    Prefetching for improved bus wrapper performance in cores. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:1, pp:58-90 [Journal]
  19. Roman L. Lysecky, Greg Stitt, Frank Vahid
    Warp Processors. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:3, pp:659-681 [Journal]
  20. Roman L. Lysecky, Susan Cotterell, Frank Vahid
    A fast on-chip profiler memory using a pipelined binary tree. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:1, pp:120-122 [Journal]
  21. Roman L. Lysecky
    Low-power warp processor for power efficient high-performance embedded systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:141-146 [Conf]
  22. Roman L. Lysecky, Frank Vahid
    A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  23. Frank Vahid, Roman L. Lysecky, Chuanjun Zhang, Greg Stitt
    Highly configurable platforms for embedded computing systems. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2003, v:34, n:11, pp:1025-1029 [Journal]

  24. Non-intrusive dynamic application profiler for detailed loop execution characterization. [Citation Graph (, )][DBLP]


  25. Hardware/software partitioning of floating point software applications to fixed-pointed coprocessor circuits. [Citation Graph (, )][DBLP]


  26. Non-intrusive dynamic application profiling for multitasked applications. [Citation Graph (, )][DBLP]


  27. Transaction-Level Modeling for Sensor Networks Using SystemC. [Citation Graph (, )][DBLP]


  28. Design space exploration for application specific FPGAS in system-on-a-chip designs. [Citation Graph (, )][DBLP]


  29. Warp Processing: Dynamic Translation of Binaries to FPGA Circuits. [Citation Graph (, )][DBLP]


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