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Srihari Makineni: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Lisa R. Hsu, Steven K. Reinhardt, Ravishankar R. Iyer, Srihari Makineni
    Communist, utilitarian, and capitalist cache policies on CMPs: caches as a shared resource. [Citation Graph (0, 0)][DBLP]
    PACT, 2006, pp:13-22 [Conf]
  2. Srihari Makineni, Ravishankar R. Iyer, Partha Sarangam, Donald Newell, Li Zhao, Ramesh Illikkal, Jaideep Moses
    Receive Side Coalescing for Accelerating TCP/IP Processing. [Citation Graph (0, 0)][DBLP]
    HiPC, 2006, pp:289-300 [Conf]
  3. Srihari Makineni, Ravi R. Iyer
    Architectural Characterization of TCP/IP Packet Processing on the Pentium M Microprocessor. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:152-163 [Conf]
  4. Li Zhao, Ravi R. Iyer, Srihari Makineni, Laxmi N. Bhuyan, Donald Newell
    Hardware Support for Bulk Data Movement in Server Platforms. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:53-60 [Conf]
  5. Keshavan Varadarajan, S. K. Nandy, Vishal Sharda, Amrutur Bharadwaj, Ravi R. Iyer, Srihari Makineni, Donald Newell
    Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:433-442 [Conf]
  6. Greg J. Regnier, Srihari Makineni, Ramesh Illikkal, Ravi R. Iyer, Dave B. Minturn, Ram Huggahalli, Donald Newell, Linda S. Cline, Annie Foong
    TCP Onloading for Data Center Servers. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2004, v:37, n:11, pp:48-58 [Journal]
  7. Lisa R. Hsu, Ravishankar R. Iyer, Srihari Makineni, Steven K. Reinhardt, Donald Newell
    Exploring the cache design space for large scale CMPs. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:4, pp:24-33 [Journal]
  8. Li Zhao, Laxmi N. Bhuyan, Ravi R. Iyer, Srihari Makineni, Donald Newell
    Hardware Support for Accelerating Data Movement in Server Platform. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:6, pp:740-753 [Journal]
  9. Ravi R. Iyer, Li Zhao, Fei Guo, Ramesh Illikkal, Srihari Makineni, Donald Newell, Yan Solihin, Lisa R. Hsu, Steven K. Reinhardt
    QoS policies and architecture for cache/memory in CMP platforms. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 2007, pp:25-36 [Conf]
  10. Ravi R. Iyer, Mahesh Bhat, Li Zhao, Ramesh Illikkal, Srihari Makineni, Michael Jones, Kumar Shiv, Donald Newell
    Exploring Small-Scale and Large-Scale CMP Architectures for Commercial Java Servers. [Citation Graph (0, 0)][DBLP]
    IISWC, 2006, pp:191-200 [Conf]
  11. Li Zhao, Ravi R. Iyer, Jaideep Moses, Ramesh Illikkal, Srihari Makineni, Donald Newell
    Exploring Large-Scale CMP Architectures Using ManySim. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:4, pp:21-33 [Journal]

  12. CacheScouts: Fine-Grain Monitoring of Shared Caches in CMP Platforms. [Citation Graph (, )][DBLP]

  13. NCID: a non-inclusive cache, inclusive directory architecture for flexible and efficient cache hierarchies. [Citation Graph (, )][DBLP]

  14. To Snoop or Not to Snoop: Evaluation of Fine-Grain and Coarse-Grain Snoop Filtering Techniques. [Citation Graph (, )][DBLP]

  15. Constraint-Aware Large-Scale CMP Cache Design. [Citation Graph (, )][DBLP]

  16. Achieving 10Gbps Network Processing: Are We There Yet?. [Citation Graph (, )][DBLP]

  17. Evaluating implications of Virtual Worlds on server architecture using Second Life. [Citation Graph (, )][DBLP]

  18. Characterization of Direct Cache Access on multi-core systems and 10GbE. [Citation Graph (, )][DBLP]

  19. Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy. [Citation Graph (, )][DBLP]

  20. Re-examining cache replacement policies. [Citation Graph (, )][DBLP]

  21. Anatomy and Performance of SSL Processing. [Citation Graph (, )][DBLP]

  22. CMPSched$im: Evaluating OS/CMP interaction on shared cache management. [Citation Graph (, )][DBLP]

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