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D. Scott Wills: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Lucian Codrescu, D. Scott Wills
    On Dynamic Speculative Thread Partitioning and the MEM-Slicing Algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1999, pp:40-46 [Conf]
  2. Jongmyon Kim, D. Scott Wills, Linda M. Wills
    Architectural Enhancements for Color Image and Video Processing on Embedded Systems. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2005, pp:104-117 [Conf]
  3. Jongmyon Kim, D. Scott Wills, Linda M. Wills
    Determining Optimal Grain Size for Efficient Vector Processing on SIMD Image Processing Architectures. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2005, pp:551-565 [Conf]
  4. Huy Cat, Myunghee Lee, Brent Buchanan, D. Scott Wills, Martin A. Brooke, Nan M. Jokerst
    Silicon VLSI processing architectures incorporating integrated optoelectronic devices. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1995, pp:17-27 [Conf]
  5. Sek M. Chai, Antonio Gentile, D. Scott Wills
    Impact of Power Density Limitation in Gigascale Integration for the SIMD Pixel Processor. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1999, pp:57-71 [Conf]
  6. Lucian Codrescu, Mondira Deb Pant, Tarek M. Taha, John Eble, D. Scott Wills, James D. Meindl
    Exploring Microprocessor Architectures for Gigascale Integration. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1999, pp:242-255 [Conf]
  7. Jongmyon Kim, D. Scott Wills
    Efficient Processing of Color Image Sequences Using a Color-Aware Instruction Set on Mobile Systems. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:137-149 [Conf]
  8. Antonio Gentile, Huy Cat, Faouzi Kossentini, Filippo Sorbello, D. Scott Wills
    Real-Time Implementation of Full-Search Vector Quantization on a Low Memory SIMD Architecture. [Citation Graph (0, 0)][DBLP]
    Data Compression Conference, 1996, pp:438- [Conf]
  9. William H. Robinson, D. Scott Will
    Cost Modeling or Early Image Processing Applications. [Citation Graph (0, 0)][DBLP]
    Workshop on Digital and Computational Video, 2001, pp:29-0 [Conf]
  10. Jongmyon Kim, D. Scott Wills, Linda M. Wills
    Implementing and Evaluating Color-Aware Instruction Set for Low-Memory, Embedded Video Processing in Data Parallel Architectures. [Citation Graph (0, 0)][DBLP]
    EUC, 2005, pp:4-16 [Conf]
  11. Santithorn Bunchua, D. Scott Wills, Linda M. Wills
    Reducing Operand Transport Complexity of Superscalar Processors using Distributed Register Files. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:532-535 [Conf]
  12. Lucian Codrescu, D. Scott Wills
    Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:428-435 [Conf]
  13. José Cruz-Rivera, D. Scott Wills, Thomas K. Gaylord, Elias N. Glytsis
    Modeling the Technology Impact on the Design of a Two-Level Multicomputer Interconnection Network. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:165-169 [Conf]
  14. William J. Dally, Andrew A. Chien, Stuart Fiske, Greg Fyler, Waldemar Horwat, John S. Keen, Richard A. Lethin, Michael D. Noakes, Peter R. Nuth, D. Scott Wills
    The Message Driven Processor: An Integrated Multicomputer Processing Element. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:416-419 [Conf]
  15. D. Scott Wills, W. Stephen Lacy, Huy Cat, Michael A. Hopper, Ashutosh Razdan, Sek M. Chai
    Pica: An Ultra-Light Processor for High-Througput Applications. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:410-414 [Conf]
  16. Antonio Gentile, D. Scott Wills
    Impact of Pixel per Processor Ratio on Embedded SIMD Architectures. [Citation Graph (0, 0)][DBLP]
    ICIAP, 2001, pp:204-208 [Conf]
  17. D. Scott Wills, Matthias Grossglauser
    A Scalable Optical Interconnection Network for Fine-Grain Parallel Architectures. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:154-157 [Conf]
  18. William J. Dally, Andrew A. Chien, Stuart Fiske, Waldemar Horwat, John S. Keen, Michael Larivee, Richard A. Lethin, Peter R. Nuth, D. Scott Wills
    The J-Machine: A Fine-Gain Concurrent Computer. [Citation Graph (0, 0)][DBLP]
    IFIP Congress, 1989, pp:1147-1153 [Conf]
  19. Antonio Gentile, José Cruz-Rivera, D. Scott Wills, Leugim Bustelo, José J. Figueroa, Javier E. Fonseca-Camacho, Wilfredo E. Lugo-Beauchamp, Ricardo Olivieri, Marlyn Quiñones-Cerpa, Alexis H. Rivera-Ríos, Iomar Vargas-Gonzáles, Michelle Viera-Vera
    Real-Time Image Processing on a Focal Plane SIMD Array. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP Workshops, 1999, pp:400-405 [Conf]
  20. Hongkyu Kim, D. Scott Wills, Linda M. Wills
    Technology-based Architectural Analysis of Operand Bypass Networks for Efficient Operand Transport. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  21. William J. Dally, Linda Chao, Andrew A. Chien, Soha Hassoun, Waldemar Horwat, Jon Kaplan, Paul Song, Brian Totty, D. Scott Wills
    Architecture of a Message-Driven Processor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1987, pp:189-196 [Conf]
  22. William J. Dally, Linda Chao, Andrew A. Chien, Soha Hassoun, Waldemar Horwat, Jon Kaplan, Paul Song, Brian Totty, D. Scott Wills
    Architecture of a Message-Driven Processor. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:337-344 [Conf]
  23. William J. Dally, Andrew A. Chien, Stuart Fiske, Waldemar Horwat, Richard A. Lethin, Michael D. Noakes, Peter R. Nuth, Ellen Spertus, Deborah A. Wallach, D. Scott Wills, Andrew Chang, John S. Keen
    Retrospective: the J-machine. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:54-58 [Conf]
  24. Jinsung Park, J. A. Tabler, Martin A. Brooke, Nan M. Jokerst, D. Scott Wills
    Adaptive digital bias control for an optical receiver and transmitter. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:323-326 [Conf]
  25. J. J. Chang, Myunghee Lee, Sungyong Jung, Martin A. Brooke, Nan M. Jokerst, D. Scott Wills
    Fully differential current-input CMOS amplifier front-end suppressing mixed signal substrate noise for optoelectronic applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:327-330 [Conf]
  26. Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Vivek Tiwari
    An architectural solution for the inductive noise problem due to clock-gating. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:255-257 [Conf]
  27. Hongkyu Kim, D. Scott Wills, Linda M. Wills
    Reducing Operand Communication Overhead using Instruction Clustering for Multimedia Application. [Citation Graph (0, 0)][DBLP]
    ISM, 2005, pp:345-352 [Conf]
  28. Jongmyon Kim, Santithorn Bunchua, D. Scott Wills
    Fast Color Image Processing Using Quantized Color Instruction Set. [Citation Graph (0, 0)][DBLP]
    ITCC, 2003, pp:529-535 [Conf]
  29. Hongkyu Kim, D. Scott Wills, Linda M. Wills
    Empirical Analysis of Operand Usage and Transport in Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:168-171 [Conf]
  30. William F. Appelbe, Srinivas Doddapaneni, Reid Harmon, Phil May, D. Scott Wills, Maurizio Vitale
    Hoisting Branch Conditions - Improving Super-Scalar Processor Performance. [Citation Graph (0, 0)][DBLP]
    LCPC, 1995, pp:304-317 [Conf]
  31. Peter G. Sassone, D. Scott Wills, Gabriel H. Loh
    Static strands: safely collapsing dependence chains for increasing embedded power efficiency. [Citation Graph (0, 0)][DBLP]
    LCTES, 2005, pp:127-136 [Conf]
  32. Peter G. Sassone, D. Scott Wills
    Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline Communication. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:7-17 [Conf]
  33. William J. Dally, D. Scott Wills
    Universal Mechanisms for Concurrency. [Citation Graph (0, 0)][DBLP]
    PARLE (1), 1989, pp:19-33 [Conf]
  34. Phil May, Sek M. Chai, D. Scott Wills
    HiPER-P: An Efficient, High-Performance Router for Multicomputer Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    PCRCW, 1997, pp:103-118 [Conf]
  35. D. Scott Wills, W. Stephen Lacy, José Cruz-Rivera
    The Offset Cube: An Optoelectronic Interconnection Network. [Citation Graph (0, 0)][DBLP]
    PCRCW, 1994, pp:86-100 [Conf]
  36. Tarek M. Taha, D. Scott Wills
    An Instruction Throughput Model of Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2003, pp:156-163 [Conf]
  37. Thomas L. Sterling, D. Scott Wills, Ellery Y. Chan
    Tokenless static data flow using associative templates. [Citation Graph (0, 0)][DBLP]
    SC, 1988, pp:70-79 [Conf]
  38. Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Vivek Tiwari
    Inductive Noise Reduction at the Architectural Level. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:162-167 [Conf]
  39. Linda M. Wills, Tarek Taha, Lewis B. Baumstark Jr., D. Scott Wills
    Estimating Potential Parallelism for Platform Retargeting. [Citation Graph (0, 0)][DBLP]
    WCRE, 2002, pp:55-64 [Conf]
  40. Antonio Gentile, Sam Sander, Linda Wills, D. Scott Wills
    The impact of grain size on the efficiency of embedded SIMD image processing architectures. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2004, v:64, n:11, pp:1318-1327 [Journal]
  41. Phil May, Myunghee Lee, Scott T. Wilkinson, Olivier Vendier, Zhuang Ho, Steven W. Bond, D. Scott Wills, Martin A. Brooke, Nan M. Jokerst, April Brown
    A 100 Mbps, LED Through-Wafer Optoelectronic Link for Multicomputer Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1997, v:41, n:1, pp:3-19 [Journal]
  42. Lucian Codrescu, D. Scott Wills
    On Dynamic Speculative Thread Partitioning and the MEM-Slicing Algorithm. [Citation Graph (0, 0)][DBLP]
    J. UCS, 2000, v:6, n:10, pp:908-927 [Journal]
  43. Lucian Codrescu, D. Scott Wills, James D. Meindl
    Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:1, pp:67-82 [Journal]
  44. Antonio Gentile, D. Scott Wills
    Portable Video Supercomputing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:8, pp:960-973 [Journal]
  45. Peter G. Sassone, D. Scott Wills
    Scaling Up the Atlas Chip-Multiprocessor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:1, pp:82-87 [Journal]
  46. Sek M. Chai, D. Scott Wills
    Systolic Opportunities for Multidimensional Data Streams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2002, v:13, n:4, pp:388-398 [Journal]
  47. W. Stephen Lacy, José Cruz-Rivera, D. Scott Wills
    The Offset Cube: A Three-Dimensional Multicomputer Network Topology Using Through-Wafer Optics. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1998, v:9, n:9, pp:893-908 [Journal]
  48. Phil May, Santithorn Bunchua, D. Scott Wills
    HiPER: A Compact Narrow Channel Router with Hop-by-Hop Error Correction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2002, v:13, n:5, pp:485-498 [Journal]
  49. D. Scott Wills, Huy Cat, José Cruz-Rivera, W. Stephen Lacy, James M. Baker Jr., John Eble, Abelardo López-Lagunas, Michael A. Hopper
    High-Throughput, Low-Memory Applications on the Pica Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1997, v:8, n:10, pp:1055-1067 [Journal]
  50. Cory Hawkins, Benjamin A. Small, D. Scott Wills, Keren Bergman
    The Data Vortex, an All Optical Path Multicomputer Interconnection Network. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2007, v:18, n:3, pp:409-420 [Journal]
  51. S. Apewokin, B. Valentine, Linda Wills, D. Scott Wills, Antonio Gentile
    Multimodal Mean Adaptive Backgrounding for Embedded Real-Time Video Surveillance. [Citation Graph (0, 0)][DBLP]
    CVPR, 2007, pp:- [Conf]
  52. Peter G. Sassone, D. Scott Wills, Gabriel H. Loh
    Static strands: Safely exposing dependence chains for increasing embedded power efficiency. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2007, v:6, n:4, pp:- [Journal]
  53. Sek M. Chai, Tarek M. Taha, D. Scott Wills, James D. Meindl
    Heterogeneous architecture models for interconnect-motivated system design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:6, pp:660-670 [Journal]
  54. Mondira Deb Pant, Pankaj Pant, D. Scott Wills
    On-chip decoupling capacitor optimization using architectural level prediction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:319-326 [Journal]
  55. Lucian Codrescu, S. Nugent, James D. Meindl, D. Scott Wills
    Modeling technology impact on cluster microprocessor performance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:909-920 [Journal]

  56. Midground object detection in real world video scenes. [Citation Graph (, )][DBLP]


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