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Jonathan Rose: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Peter Yiannacouras, Jonathan Rose, J. Gregory Steffan
    The microarchitecture of FPGA-based soft processors. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:202-212 [Conf]
  2. Ahmad Darabiha, Jonathan Rose, W. James MacLean
    Video-Rate Stereo Depth Measurement on Programmable Hardware. [Citation Graph (0, 0)][DBLP]
    CVPR (1), 2003, pp:203-210 [Conf]
  3. Kevin Chung, Jonathan Rose
    TEMPT: Technology Mapping for the Exploration of FPGA Architectures with Hard-Wired Connections. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:361-367 [Conf]
  4. Robert J. Francis, Jonathan Rose, Kevin Chung
    Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:613-619 [Conf]
  5. Robert J. Francis, Jonathan Rose, Zvonko G. Vranesic
    Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:227-233 [Conf]
  6. Michael D. Hutton, Jerry P. Grossman, Jonathan Rose, Derek G. Corneil
    Characterization and Parameterized Random Generation of Digital Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:94-99 [Conf]
  7. Jonathan Rose
    LocusRoute: A Parallel Global Router for Standard Cells. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:189-195 [Conf]
  8. Jonathan Rose
    Will the Field-Programmable Gata Array Replace the Mask-Programmable Gate Array? (Panel Abstract). [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:779- [Conf]
  9. Jonathan Rose
    Logic Emulation: A Niche or a Future Standard for Design Verification? (Panel Abstract). [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:164- [Conf]
  10. Rob A. Rutenbar, Max Baron, Thomas Daniel, Rajeev Jayaraman, Zvi Or-Bach, Jonathan Rose, Carl Sechen
    Panel: (When) Will FPGAs Kill ASICs? [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:321-322 [Conf]
  11. Elias Ahmed, Jonathan Rose
    The effect of LUT and cluster size on deep-submicron FPGA performance and density. [Citation Graph (0, 0)][DBLP]
    FPGA, 2000, pp:3-12 [Conf]
  12. William Chow, Jonathan Rose
    EVE: a CAD tool for manual placement and pipelining assistance of FPGA circuits. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:85-94 [Conf]
  13. Vaughn Betz, Jonathan Rose
    Automatic generation of FPGA routing architectures from high-level descriptions. [Citation Graph (0, 0)][DBLP]
    FPGA, 2000, pp:175-184 [Conf]
  14. Tomasz S. Czajkowski, Jonathan Rose
    A synthesis oriented omniscient manual editor. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:89-98 [Conf]
  15. Vaughn Betz, Jonathan Rose
    Using Architectural ``Families'' to Increase FPGA Speed and Density. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:10-16 [Conf]
  16. Vaughn Betz, Jonathan Rose
    FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:59-68 [Conf]
  17. Andy Gean Ye, Jonathan Rose
    Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:3-13 [Conf]
  18. Mohammed A. S. Khalid, Jonathan Rose
    A Hybrid Complete-Graph Partial-Crossbar Routing Architecture for Multi-FPGA Systems. [Citation Graph (0, 0)][DBLP]
    FPGA, 1998, pp:45-54 [Conf]
  19. Paul D. Kundarewich, Jonathan Rose
    Synthetic circuit generation using clustering and iteration. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:245- [Conf]
  20. Ian Kuon, Aaron Egier, Jonathan Rose
    Transistor grouping and metal layer trade-offs in automatic tile layout of FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:249- [Conf]
  21. Ian Kuon, Aaron Egier, Jonathan Rose
    Design, layout and verification of an FPGA using automated tools. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:215-226 [Conf]
  22. Ian Kuon, Jonathan Rose
    Measuring the gap between FPGAs and ASICs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2006, pp:21-30 [Conf]
  23. Michael D. Hutton, Jonathan Rose, Derek G. Corneil
    Generation of Synthetic Sequential Benchmark Circuits. [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:149-155 [Conf]
  24. David M. Lewis, Vaughn Betz, David Jefferson, Andy Lee, Christopher Lane, Paul Leventis, Sandy Marquardt, Cameron McClintock, Bruce Pedersen, Giles Powell, Srinivas Reddy, Chris Wysocki, Richard Cliff, Jonathan Rose
    The StratixTM routing and logic architecture. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:12-20 [Conf]
  25. David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow
    The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System. [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:53-61 [Conf]
  26. David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose
    The Stratix II logic and routing architecture. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:14-20 [Conf]
  27. Alexander Marquardt, Vaughn Betz, Jonathan Rose
    Timing-driven placement for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2000, pp:203-213 [Conf]
  28. Alexander Marquardt, Vaughn Betz, Jonathan Rose
    Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:37-46 [Conf]
  29. Jonathan Rose, Dwight D. Hill
    Architectural and Physical Design Challenges for One-Million Gate FPGAs and Beyond. [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:129-132 [Conf]
  30. Jonathan Rose, Sinan Kaptanoglu, Clive McCarthy, Rob Smith, Sandip Vij, Steve Taylor
    Constraints from Hell: How to Tell Makes a Good FPGA (Panel). [Citation Graph (0, 0)][DBLP]
    FPGA, 1998, pp:117-119 [Conf]
  31. Rob McCready, Jonathan Rose
    Real-time, frame-rate face detection on a configurable hardware system (poster abstract). [Citation Graph (0, 0)][DBLP]
    FPGA, 2000, pp:221- [Conf]
  32. Yaska Sankar, Jonathan Rose
    Trading Quality for Compile Time: Ultra-Fast Placement for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:157-166 [Conf]
  33. Mike Sheng, Jonathan Rose
    Mixing buffers and pass transistors in FPGA routing architectures. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:75-84 [Conf]
  34. Ketan Padalia, Ryan Fung, Mark Bourgeault, Aaron Egier, Jonathan Rose
    Automatic transistor and physical design of FPGA tiles from an architectural specification. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:164-172 [Conf]
  35. Jordan S. Swartz, Vaughn Betz, Jonathan Rose
    A Fast Routability-Driven Router for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1998, pp:140-149 [Conf]
  36. Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose
    Application-specific customization of soft processor microarchitecture. [Citation Graph (0, 0)][DBLP]
    FPGA, 2006, pp:201-210 [Conf]
  37. Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
    Architecture of Centralized Field-Configurable Memory. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:97-103 [Conf]
  38. Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
    Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays. [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:10-16 [Conf]
  39. Vaughn Betz, Jonathan Rose
    VPR: A new packing, placement and routing tool for FPGA research. [Citation Graph (0, 0)][DBLP]
    FPL, 1997, pp:213-222 [Conf]
  40. Anish Alex, Jonathan Rose, Ruth Isserlin-Weinberger, Christopher W. V. Hogue
    Hardware Accelerated Novel Protein Identification. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:13-22 [Conf]
  41. Andy Gean Ye, Jonathan Rose
    Measuring and Utilizing the Correlation Between Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit Building Blocks. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:159-166 [Conf]
  42. Peter Jamieson, Jonathan Rose
    A Verilog RTL Synthesis Tool for Heterogeneous FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:305-310 [Conf]
  43. Joshua Fender, Jonathan Rose, David R. Galloway
    The Transmogrifier-4: An FPGA-Based Hardware Development System with Multi-Gigabyte Memory Capacity and High Host and Memory Bandwidth. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:301-302 [Conf]
  44. Vaughn Betz, Jonathan Rose
    Directional bias and non-uniformity in FPGA global routing architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:652-659 [Conf]
  45. Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic
    A Detailed Router for Field-Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:382-385 [Conf]
  46. Robert J. Francis, Jonathan Rose, Zvonko G. Vranesic
    Technology Mapping on Lookup Table-Based FPGAs for Performance. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:568-571 [Conf]
  47. David Karchmer, Jonathan Rose
    Definition and solution of the memory packing problem for field-programmable systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:20-26 [Conf]
  48. Benjamin Tseng, Jonathan Rose, Stephen Dean Brown
    Improving FPGA Routing Architectures Using Architecture and CAD Interactions. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:99-104 [Conf]
  49. Mohammed A. S. Khalid, Jonathan Rose
    Hardwired-Clusters Partial-Crossbar: A Hierarchical Routing Architecture for Multi-FPGA Systems. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP Workshops, 1999, pp:597-605 [Conf]
  50. Michael D. Hutton, Jonathan Rose
    Equivalence classes of clone circuits for physical-design benchmarking. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:428-431 [Conf]
  51. Michael D. Hutton, Jonathan Rose
    Applications of clone circuits to issues in physical-design. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:448-451 [Conf]
  52. Jonathan Rose
    Hard vs. Soft: The Central Question of Pre-Fabricated Silicon. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2004, pp:2-5 [Conf]
  53. Jonathan Rose
    The Parallel Decomposition and Implementation of an Integrated Circuit Global Router. [Citation Graph (0, 0)][DBLP]
    PPOPP/PPEALS, 1988, pp:138-145 [Conf]
  54. Vaughn Betz, Jonathan Rose
    How Much Logic Should Go in an FPGA Logic Block? [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:1, pp:10-15 [Journal]
  55. Stephen Dean Brown, Jonathan Rose
    FPGA and CPLD Architectures: A Tutorial. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:2, pp:42-57 [Journal]
  56. Ahmad Darabiha, W. James MacLean, Jonathan Rose
    Reconfigurable hardware implementation of a phase-correlation stereoalgorithm. [Citation Graph (0, 0)][DBLP]
    Mach. Vis. Appl., 2006, v:17, n:2, pp:116-132 [Journal]
  57. Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic
    A detailed router for field-programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:5, pp:620-628 [Journal]
  58. Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic
    A stochastic model to predict the routability of field-programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:12, pp:1827-1838 [Journal]
  59. Michael D. Hutton, Jonathan Rose, Derek G. Corneil
    Automatic generation of synthetic sequential benchmark circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:8, pp:928-940 [Journal]
  60. Michael D. Hutton, Jonathan Rose, Jerry P. Grossman, Derek G. Corneil
    Characterization and parameterized generation of synthetic combinational benchmark circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:10, pp:985-996 [Journal]
  61. Paul D. Kundarewich, Jonathan Rose
    Synthetic circuit generation using clustering and iteration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:869-887 [Journal]
  62. Jonathan Rose
    Parallel global routing for standard cells. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:10, pp:1085-1095 [Journal]
  63. Jonathan Rose, Wolfgang Klebsch, Jürgen Wolf
    Temperature measurement and equilibrium dynamics of simulated annealing placements. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:3, pp:253-259 [Journal]
  64. Jonathan Rose, W. Martin Snelgrove, Zvonko G. Vranesic
    Parallel standard cell placement algorithms with quality equivalent to simulated annealing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:3, pp:387-396 [Journal]
  65. Elias Ahmed, Jonathan Rose
    The effect of LUT and cluster size on deep-submicron FPGA performance and density. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:3, pp:288-298 [Journal]
  66. Vaughn Betz, Jonathan Rose
    Effect of the prefabricated routing track distribution on FPGA area-efficiency. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:445-456 [Journal]
  67. David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow
    The Transmogrifier-2: a 1 million gate rapid-prototyping system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:188-198 [Journal]
  68. Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
    The memory/logic interface in FPGAs with large embedded memory arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:80-91 [Journal]
  69. Mohammed A. S. Khalid, Jonathan Rose
    A novel and efficient routing architecture for multi-FPGA systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:1, pp:30-39 [Journal]
  70. Alexander Marquardt, Vaughn Betz, Jonathan Rose
    Speed and area tradeoffs in cluster-based FPGA architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:1, pp:84-93 [Journal]
  71. Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
    Structural analysis and generation of synthetic digital circuits with memory. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:223-226 [Journal]

  72. VESPA: portable, scalable, and flexible FPGA-based vector processors. [Citation Graph (, )][DBLP]


  73. Fine-grain performance scaling of soft vector processors. [Citation Graph (, )][DBLP]


  74. Automated transistor sizing for FPGA architecture exploration. [Citation Graph (, )][DBLP]


  75. FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy. [Citation Graph (, )][DBLP]


  76. Modeling routing demand for early-stage FPGA architecture development. [Citation Graph (, )][DBLP]


  77. Area and delay trade-offs in the circuit and architecture design of FPGAs. [Citation Graph (, )][DBLP]


  78. Soft vector processors vs FPGA custom hardware: measuring and reducing the gap. [Citation Graph (, )][DBLP]


  79. VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling. [Citation Graph (, )][DBLP]


  80. The evolution of architecture exploration of programmable devices. [Citation Graph (, )][DBLP]


  81. Data parallel FPGA workloads: Software versus hardware. [Citation Graph (, )][DBLP]


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