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Publications of Author

1. Duo Liu, Bei Hua, Xianghui Hu, Xinan Tang
   High-performance packet classification algorithm for many-core and multithreaded network processor. [Citation Graph (0, 0)][DBLP]
   CASES, 2006, pp:334-344 [Conf]
   
2. Richard Pon, Maxim A. Batalin, Victor Chen, Aman Kansal, Duo Liu, Mohammad H. Rahimi, Lisa Shirachi, Arun Somasundra, Yan Yu, Mark M. Hansen, William J. Kaiser, Mani B. Srivastava, Gaurav S. Sukhatme, Deborah Estrin
   Coordinated Static and Mobile Sensing for Environmental Monitoring. [Citation Graph (0, 0)][DBLP]
   DCOSS, 2005, pp:403-405 [Conf]
   
3. Richard Pon, Maxim A. Batalin, Jason Gordon, Aman Kansal, Duo Liu, Mohammad H. Rahimi, Lisa Shirachi, Yan Yu, Mark M. Hansen, William J. Kaiser, Mani B. Srivastava, Gaurav S. Sukhatme, Deborah Estrin
   Networked infomechanical systems: a mobile embedded networked sensor platform. [Citation Graph (0, 0)][DBLP]
   IPSN, 2005, pp:376-381 [Conf]
   
4. Maxim A. Batalin, Mohammad H. Rahimi, Yan Yu, Duo Liu, Aman Kansal, Gaurav S. Sukhatme, William J. Kaiser, Mark M. Hansen, Gregory J. Pottie, Mani B. Srivastava, Deborah Estrin
   Call and response: experiments in sampling the environment. [Citation Graph (0, 0)][DBLP]
   SenSys, 2004, pp:25-38 [Conf]
   
5. Duo Liu, Ping Luo, Yi-Qi Dai
   Attack on Digital Multi-Signature Scheme Based on Elliptic Curve Cryptosystem. [Citation Graph (0, 0)][DBLP]
   J. Comput. Sci. Technol., 2007, v:22, n:1, pp:92-94 [Journal]
   
6. 
   Optimal loop parallelization for maximizing iteration-level parallelism. [Citation Graph (, )][DBLP]
   
   
7. 
   New Elliptic Curve Multi-scalar Multiplication Algorithm for a Pair of Integers to Resist SPA. [Citation Graph (, )][DBLP]
   
   
8. 
   RNFTL: a reuse-aware NAND flash translation layer for flash memory. [Citation Graph (, )][DBLP]
   
   
9. 
   Removal of misbehaving insiders in anonymous VANETs. [Citation Graph (, )][DBLP]
   
   
10. 
    Optimal Task Scheduling by Removing Inter-Core Communication Overhead for Streaming Applications on MPSoC. [Citation Graph (, )][DBLP]
    
    
11. 
    Loop scheduling with memory access reduction under register constraints for DSP applications. [Citation Graph (, )][DBLP]